From patchwork Thu Jan 15 07:39:24 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Xiantao" X-Patchwork-Id: 2436 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n0F7a6eF025742 for ; Wed, 14 Jan 2009 23:36:06 -0800 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1762362AbZAOHjl (ORCPT ); Thu, 15 Jan 2009 02:39:41 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1762704AbZAOHjk (ORCPT ); Thu, 15 Jan 2009 02:39:40 -0500 Received: from mga03.intel.com ([143.182.124.21]:59015 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1762661AbZAOHjj convert rfc822-to-8bit (ORCPT ); Thu, 15 Jan 2009 02:39:39 -0500 Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga101.ch.intel.com with ESMTP; 14 Jan 2009 23:39:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.37,268,1231142400"; d="scan'208";a="100214000" Received: from fmsmsxpoc001.amr.corp.intel.com ([132.233.49.22]) by azsmga001.ch.intel.com with ESMTP; 14 Jan 2009 23:39:36 -0800 Received: from fmsmsxTAP001.amr.corp.intel.com (10.19.9.33) by fmsmsxpoc001.amr.corp.intel.com (132.233.49.22) with Microsoft SMTP Server (TLS) id 8.1.311.2; Wed, 14 Jan 2009 23:39:28 -0800 Received: from pdsmsx602.ccr.corp.intel.com (172.16.12.184) by fmsmsxTAP001.amr.corp.intel.com (10.19.9.33) with Microsoft SMTP Server (TLS) id 8.1.311.2; Wed, 14 Jan 2009 23:39:27 -0800 Received: from pdsmsx503.ccr.corp.intel.com ([172.16.12.95]) by pdsmsx602.ccr.corp.intel.com ([172.16.12.184]) with mapi; Thu, 15 Jan 2009 15:39:26 +0800 From: "Zhang, Xiantao" To: "Zhang, Yang" , "kvm-ia64@vger.kernel.org" CC: "kvm@vger.kernel.org" , Avi Kivity Date: Thu, 15 Jan 2009 15:39:24 +0800 Subject: RE: [PATCH] KVM: IA64: fix fp fault/trap handler Thread-Topic: [PATCH] KVM: IA64: fix fp fault/trap handler Thread-Index: Acl2J7n7TLO2rNP/TYudYEF01OQEAAAvIKhA Message-ID: <706158FABBBA044BAD4FE898A02E4BC21F50E9F0@pdsmsx503.ccr.corp.intel.com> References: <10C63FAD690C13458F0B32BCED571F1403D7491A@pdsmsx502.ccr.corp.intel.com> In-Reply-To: <10C63FAD690C13458F0B32BCED571F1403D7491A@pdsmsx502.ccr.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Avi, Please help to commit this patch if no other comments, and queue it for 2.6.29 fixes. Thanks! Xiantao -----Original Message----- From: Zhang, Yang Sent: Wednesday, January 14, 2009 5:09 PM To: kvm-ia64@vger.kernel.org Cc: kvm@vger.kernel.org; Avi Kivity; Zhang, Xiantao Subject: [PATCH] KVM: IA64: fix fp fault/trap handler Hi Please help me to review it. Best Regards --yang From 9035b13377119cd7019f7e27624491dcb5e1c2d0 Mon Sep 17 00:00:00 2001 From: Yang Zhang Date: Thu, 8 Jan 2009 15:13:31 +0800 Subject: [PATCH] KVM: IA64: fix fp fault/trap handler The floating-point registers f6-f11 is used by vmm and saved in kvm-pt-regs, so should set the correct bit mask and the pointer in fp_state, otherwise, fpswa may touch vmm's fp registers instead of guests'. In addition, for fp trap handling, since the instruction which leads to fp trap is completely executed, so can't use retry machanism to re-execute it, because it may pollute some registers. Signed-off-by: Yang Zhang --- arch/ia64/kvm/process.c | 17 +++++++++-------- 1 files changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/ia64/kvm/process.c b/arch/ia64/kvm/process.c index 552d077..c84ef13 100644 --- a/arch/ia64/kvm/process.c +++ b/arch/ia64/kvm/process.c @@ -455,13 +455,18 @@ fpswa_ret_t vmm_fp_emulate(int fp_fault, void *bundle, unsigned long *ipsr, if (!vmm_fpswa_interface) return (fpswa_ret_t) {-1, 0, 0, 0}; - /* - * Just let fpswa driver to use hardware fp registers. - * No fp register is valid in memory. - */ memset(&fp_state, 0, sizeof(fp_state_t)); /* + * compute fp_state. only FP registers f6 - f11 are used by the + * vmm, so set those bits in the mask and set the low volatile + * pointer to point to these registers. + */ + fp_state.bitmask_low64 = 0xfc0; /* bit6..bit11 */ + + fp_state.fp_state_low_volatile = (fp_state_low_volatile_t *) ®s->f6; + + /* * unsigned long (*EFI_FPSWA) ( * unsigned long trap_type, * void *Bundle, @@ -545,10 +550,6 @@ void reflect_interruption(u64 ifa, u64 isr, u64 iim, status = vmm_handle_fpu_swa(0, regs, isr); if (!status) return ; - else if (-EAGAIN == status) { - vcpu_decrement_iip(vcpu); - return ; - } break; }