From patchwork Mon Nov 16 18:26:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 11910373 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12E0FC55ABD for ; Mon, 16 Nov 2020 18:30:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BE6FF2231B for ; Mon, 16 Nov 2020 18:30:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388478AbgKPS3f (ORCPT ); Mon, 16 Nov 2020 13:29:35 -0500 Received: from mga02.intel.com ([134.134.136.20]:48448 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388296AbgKPS2S (ORCPT ); Mon, 16 Nov 2020 13:28:18 -0500 IronPort-SDR: PcUpB1VtxuHYlEa4fLYRvbx/qwmu5nm7RKQIKF6cLe4Gee1uvDqqR7Rwn0AIF0Y55NiIDYZWU2 W7fkfXhLWE2Q== X-IronPort-AV: E=McAfee;i="6000,8403,9807"; a="157819189" X-IronPort-AV: E=Sophos;i="5.77,483,1596524400"; d="scan'208";a="157819189" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2020 10:28:18 -0800 IronPort-SDR: GGz46BLE+1CSeSwbw1SfIA+tXn/PkoV4eAywjZirIFZmcH9evOtMGgfHKwT4MmL1kxx5hYjvNl CoHzMwlKh06A== X-IronPort-AV: E=Sophos;i="5.77,483,1596524400"; d="scan'208";a="400528308" Received: from ls.sc.intel.com (HELO localhost) ([143.183.96.54]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2020 10:28:17 -0800 From: isaku.yamahata@intel.com To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H . Peter Anvin" , Paolo Bonzini , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, Kai Huang Subject: [RFC PATCH 55/67] KVM: TDX: Add SEAMRR related MSRs macro definition Date: Mon, 16 Nov 2020 10:26:40 -0800 Message-Id: <7e03253675d49ee0d4af5ade35752e59147a3c69.1605232743.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Kai Huang Two new MSRs IA32_SEAMRR_PHYS_BASE and IA32_SEAMRR_PHYS_MASK are added in SPR for TDX. Add macro definition for both of them. Signed-off-by: Kai Huang --- arch/x86/include/asm/msr-index.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index aad12236b33c..f42da6b11b42 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -924,4 +924,12 @@ #define MSR_VM_IGNNE 0xc0010115 #define MSR_VM_HSAVE_PA 0xc0010117 +/* Intel SEAMRR */ +#define MSR_IA32_SEAMRR_PHYS_BASE 0x00001400 +#define MSR_IA32_SEAMRR_PHYS_MASK 0x00001401 + +#define MSR_IA32_SEAMRR_PHYS_BASE_CONFIGURED (1ULL << 3) +#define MSR_IA32_SEAMRR_PHYS_MASK_ENABLED (1ULL << 11) +#define MSR_IA32_SEAMRR_PHYS_MASK_LOCKED (1ULL << 10) + #endif /* _ASM_X86_MSR_INDEX_H */