From patchwork Mon Jan 22 23:53:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 13526464 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 237645FB80; Mon, 22 Jan 2024 23:55:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705967730; cv=none; b=FG0HU89jIggva14jOWFZrRCNqnI3M5nKNuoaTgh5XvXS+9novdTm+P4Dk3avyRYgQ2Ew9ycTXo2hbk+FXJagL3yERWsROg0Y807h5nRGqWENWJRI0dg5Ntiw4JxrFJtukYb3zN86qJH/UrM0lkFeXv166I/lJV0sdl7k73rnPr0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705967730; c=relaxed/simple; bh=oQj7us7q3FR7iciI/KFvHntTbSJoyyyxGgw23IGrLK0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=o30SH0StbybvIxeTdV6V3YU+bZgIapB9kDNcRnrlLnNX4cvnAV239bTdgCoDhxaOks/M1xYhR6Y1bARMUC/PT48W7ozeACWFgcHElDXrqp7guxX9Z4au1KCPPcq7kR1F7U2Gi0crSMBzhw82LvvDtMyncdFENNo/o883Nzvrlq4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=EJX9jA7p; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EJX9jA7p" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1705967729; x=1737503729; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=oQj7us7q3FR7iciI/KFvHntTbSJoyyyxGgw23IGrLK0=; b=EJX9jA7pilfR2k75tkRwl5lijOgfB2S44bPsrzhJ/HlKgtFzNZdsyEqq Xom13F9K7yNjWvArfNXNYsXD29tYMSwdWdnja5VFHILoPYYakQn7e1utN CE5KCn2/kvk54sUsV4q5W0NX8FAKnyfOQ/RIU0qvjIHuzy2qc6FQ+mBg2 EC4vn4vjgfmJ3pRX8CrJTJLocb9S3hka8600c/EUA+SNUFWFI4PISPlmp cnxsAZBGYIQhyjWrlVZsRf3kLdNbF9XBpegOe30iiGSxNkaeuwqw/c15+ N54agYYv//NxkwQs+mbsyiF+5y+bdsPG7IE0qJ+s/PokbTVhZ5TPo6p/h A==; X-IronPort-AV: E=McAfee;i="6600,9927,10961"; a="8016352" X-IronPort-AV: E=Sophos;i="6.05,212,1701158400"; d="scan'208";a="8016352" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2024 15:55:29 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,212,1701158400"; d="scan'208";a="1468076" Received: from ls.sc.intel.com (HELO localhost) ([172.25.112.31]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2024 15:55:28 -0800 From: isaku.yamahata@intel.com To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, Paolo Bonzini , erdemaktas@google.com, Sean Christopherson , Sagi Shahar , Kai Huang , chen.bo@intel.com, hang.yuan@intel.com, tina.zhang@intel.com Subject: [PATCH v18 040/121] KVM: x86/mmu: Disallow fast page fault on private GPA Date: Mon, 22 Jan 2024 15:53:16 -0800 Message-Id: <91c797997b57056224571e22362321a23947172f.1705965635.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Isaku Yamahata TDX requires TDX SEAMCALL to operate Secure EPT instead of direct memory access and TDX SEAMCALL is heavy operation. Fast page fault on private GPA doesn't make sense. Disallow fast page fault on private GPA. Signed-off-by: Isaku Yamahata Reviewed-by: Paolo Bonzini Reviewed-by: Binbin Wu --- arch/x86/kvm/mmu/mmu.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index b2924bd9b668..54d4c8f1ba68 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -3339,8 +3339,16 @@ static int kvm_handle_noslot_fault(struct kvm_vcpu *vcpu, return RET_PF_CONTINUE; } -static bool page_fault_can_be_fast(struct kvm_page_fault *fault) +static bool page_fault_can_be_fast(struct kvm *kvm, struct kvm_page_fault *fault) { + /* + * TDX private mapping doesn't support fast page fault because the EPT + * entry is read/written with TDX SEAMCALLs instead of direct memory + * access. + */ + if (kvm_is_private_gpa(kvm, fault->addr)) + return false; + /* * Page faults with reserved bits set, i.e. faults on MMIO SPTEs, only * reach the common page fault handler if the SPTE has an invalid MMIO @@ -3450,7 +3458,7 @@ static int fast_page_fault(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault) u64 *sptep; uint retry_count = 0; - if (!page_fault_can_be_fast(fault)) + if (!page_fault_can_be_fast(vcpu->kvm, fault)) return ret; walk_shadow_page_lockless_begin(vcpu);