From patchwork Tue Nov 7 14:56:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 13448973 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B92F035882 for ; Tue, 7 Nov 2023 15:00:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="PMrGAAEw" Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1B0413AB6; Tue, 7 Nov 2023 06:59:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699369176; x=1730905176; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sqijWJVdaQ0p2+QOCmITv7s/CttNRph7PHWJy9iU8dc=; b=PMrGAAEwUWRtTwmivl+AKpQo6RPbxHRu3jyus+xC0ziRobjqTl0HyCEv 9J4tOo5bIpLHLsV8MF+ijKCXwvdc9bZjPZKoV0c9e+PaPlcjZvcHVcD2g T2aPezShYhnyx9ums1OJvci7MPxIdyUegmPrWT+93MbxWg1zs0skh0VUR MKIJ6+Eas/koCG3MPeCOMsgTQKFVwX1YnHaXKZ7RUJl9A+UrqvUUmlrcl bk3Ftyx2QsklUAkdxBDlFGh02mv11xfylkGgg483jGOjABmY40/Pzmb1g Cq9QprWfhdI9f1L/sgfJNL+4NbvHiFViKCowGtUOxMICbRLctsJ8t5b37 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10887"; a="2462400" X-IronPort-AV: E=Sophos;i="6.03,284,1694761200"; d="scan'208";a="2462400" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2023 06:58:17 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,284,1694761200"; d="scan'208";a="10851435" Received: from ls.sc.intel.com (HELO localhost) ([172.25.112.31]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2023 06:58:16 -0800 From: isaku.yamahata@intel.com To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, Paolo Bonzini , erdemaktas@google.com, Sean Christopherson , Sagi Shahar , David Matlack , Kai Huang , Zhi Wang , chen.bo@intel.com, hang.yuan@intel.com, tina.zhang@intel.com, Sean Christopherson Subject: [PATCH v17 058/116] KVM: x86/mmu: Introduce kvm_mmu_map_tdp_page() for use by TDX Date: Tue, 7 Nov 2023 06:56:24 -0800 Message-Id: <9d87ffa2588c810b2a12ed0ac776b78283a18ac9.1699368322.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Sean Christopherson Introduce a helper to directly (pun intended) fault-in a TDP page without having to go through the full page fault path. This allows TDX to get the resulting pfn and also allows the RET_PF_* enums to stay in mmu.c where they belong. Signed-off-by: Sean Christopherson Signed-off-by: Isaku Yamahata --- v14 -> v15: - Remove loop in kvm_mmu_map_tdp_page() and return error code based on RET_FP_xxx value to avoid potential infinite loop. The caller should loop on -EAGAIN instead now. --- arch/x86/kvm/mmu.h | 3 +++ arch/x86/kvm/mmu/mmu.c | 57 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h index be3af0915b20..8ecd75528b37 100644 --- a/arch/x86/kvm/mmu.h +++ b/arch/x86/kvm/mmu.h @@ -176,6 +176,9 @@ static inline void kvm_mmu_refresh_passthrough_bits(struct kvm_vcpu *vcpu, __kvm_mmu_refresh_passthrough_bits(vcpu, mmu); } +int kvm_mmu_map_tdp_page(struct kvm_vcpu *vcpu, gpa_t gpa, u64 error_code, + int max_level); + /* * Check if a given access (described through the I/D, W/R and U/S bits of a * page fault error code pfec) causes a permission fault with the given PTE diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index 44d9c3d2f7d9..12f90116358e 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -4639,6 +4639,63 @@ int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, struct kvm_page_fault *fault) return direct_page_fault(vcpu, fault); } +int kvm_mmu_map_tdp_page(struct kvm_vcpu *vcpu, gpa_t gpa, u64 error_code, + int max_level) +{ + int r; + struct kvm_page_fault fault = (struct kvm_page_fault) { + .addr = gpa, + .error_code = error_code, + .exec = error_code & PFERR_FETCH_MASK, + .write = error_code & PFERR_WRITE_MASK, + .present = error_code & PFERR_PRESENT_MASK, + .rsvd = error_code & PFERR_RSVD_MASK, + .user = error_code & PFERR_USER_MASK, + .prefetch = false, + .is_tdp = true, + .is_private = error_code & PFERR_GUEST_ENC_MASK, + .nx_huge_page_workaround_enabled = is_nx_huge_page_enabled(vcpu->kvm), + }; + + WARN_ON_ONCE(!vcpu->arch.mmu->root_role.direct); + fault.gfn = gpa_to_gfn(fault.addr) & ~kvm_gfn_shared_mask(vcpu->kvm); + fault.slot = kvm_vcpu_gfn_to_memslot(vcpu, fault.gfn); + + r = mmu_topup_memory_caches(vcpu, false); + if (r) + return r; + + fault.max_level = max_level; + fault.req_level = PG_LEVEL_4K; + fault.goal_level = PG_LEVEL_4K; + +#ifdef CONFIG_X86_64 + if (tdp_mmu_enabled) + r = kvm_tdp_mmu_page_fault(vcpu, &fault); + else +#endif + r = direct_page_fault(vcpu, &fault); + + if (is_error_noslot_pfn(fault.pfn) || vcpu->kvm->vm_bugged) + return -EFAULT; + + switch (r) { + case RET_PF_RETRY: + return -EAGAIN; + + case RET_PF_FIXED: + case RET_PF_SPURIOUS: + return 0; + + case RET_PF_CONTINUE: + case RET_PF_EMULATE: + case RET_PF_INVALID: + default: + return -EIO; + } +} +EXPORT_SYMBOL_GPL(kvm_mmu_map_tdp_page); + static void nonpaging_init_context(struct kvm_mmu *context) { context->page_fault = nonpaging_page_fault;