| Message ID | C4F7CD9A92DBFF48AD8779355CD4D7890D792D@exchsg04.s3graphics.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 04/13/2011 06:26 AM, BrillyWu@viatech.com.cn wrote: > The CPUIDs for Centaur are added, and then the features of PadLock > hardware > engine on VIA CPU, such as "ace", "ace_en" and so on, can be passed into > the > kvm guest. > Nice to see this. Please post a link to the documentation describing these features. > > + /* cpuid 0xC0000001.edx */ > + const u32 kvm_supported_word5_x86_features = > + F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | > + F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | > + F(PMM) | F(PMM_EN); > + Are all of these features save wrt save/restore? (do they all act on state in standard registers?) Do they need any control register bits to be active or MSRs to configure? > @@ -2484,6 +2504,17 @@ static int kvm_dev_ioctl_get_supported_c > > r = -E2BIG; > if (nent>= cpuid->nent) > + goto out_free; > + > + /* Add support for Centaur's CPUID instruction. */ > + do_cpuid_ent(&cpuid_entries[nent], 0xC0000000, 0,&nent, > cpuid->nent); nent overflow check missing here. Also, should probably skip if not a Via. > + limit = cpuid_entries[nent - 1].eax; > + for (func = 0xC0000001; func<= limit&& nent< cpuid->nent; > ++func) > + do_cpuid_ent(&cpuid_entries[nent], func, 0, > + &nent, cpuid->nent); > + > + r = -E2BIG; > + if (nent>= cpuid->nent) > goto out_free; > > do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, > &nent,
On 04/13/2011 06:26 AM, BrillyWu@viatech.com.cn wrote: >> The CPUIDs for Centaur are added, and then the features of PadLock >> hardware engine on VIA CPU, such as "ace", "ace_en" and so on, can be >> passed into the kvm guest. >> > Nice to see this. Please post a link to the documentation describing > these features. These features are defined in Linux Kernel (arch/x86/include/asm/cpufeature.h), and the description for these features can be found at the following address: http://www.via.com.tw/en/initiatives/padlock/hardware.jsp >> >> + /* cpuid 0xC0000001.edx */ >> + const u32 kvm_supported_word5_x86_features = >> + F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | >> + F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | >> + F(PMM) | F(PMM_EN); >> + > Are all of these features save wrt save/restore? (do they all act on > state in standard registers?) Do they need any control register bits > to be active or MSRs to configure? These features depend on instructions for the PadLock hardware engine of VIA CPU. The PadLock instructions just act on standard registers like general X86 instructions, and the features have been enabled when the CPU leave the factory, so there is no need to activate any control register bits or configure MSRs. >> @@ -2484,6 +2504,17 @@ static int kvm_dev_ioctl_get_supported_c >> >> r = -E2BIG; >> if (nent>= cpuid->nent) >> + goto out_free; >> + >> + /* Add support for Centaur's CPUID instruction. */ >> + do_cpuid_ent(&cpuid_entries[nent], 0xC0000000, 0,&nent, >> cpuid->nent); > nent overflow check missing here. Also, should probably skip if not a Via. If not a VIA, the "limit" will be "0", so the following cycle can not run. Moreover, it seems that there is no method to know whther the CPU is a VIA or not in this function. The nent overflow check is put after the cycle like the "0x8000000" case, and when on a VIA, the returned "limit" is not large (generally it is 0xC0000004), is it neccesary to add a more check here? > + limit = cpuid_entries[nent - 1].eax; > + for (func = 0xC0000001; func<= limit&& nent< cpuid->nent; > ++func) > + do_cpuid_ent(&cpuid_entries[nent], func, 0, > + &nent, cpuid->nent); > + > + r = -E2BIG; > + if (nent>= cpuid->nent) > goto out_free; > > do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent, -- error compiling committee.c: too many arguments to function -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 04/13/2011 02:05 PM, BrillyWu@viatech.com.cn wrote: > >> > >> + /* cpuid 0xC0000001.edx */ > >> + const u32 kvm_supported_word5_x86_features = > >> + F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | > >> + F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | > >> + F(PMM) | F(PMM_EN); > >> + > > > Are all of these features save wrt save/restore? (do they all act on > > state in standard registers?) Do they need any control register bits > > to be active or MSRs to configure? > > These features depend on instructions for the PadLock hardware engine of VIA CPU. > The PadLock instructions just act on standard registers like general X86 instructions, and the features have been enabled when the CPU leave the factory, so there is no need to activate any control register bits or configure MSRs. I see there is a dependency on EFLAGS[30]. Does a VM entry clear this bit? If not, we have to do it ourselves. > >> @@ -2484,6 +2504,17 @@ static int kvm_dev_ioctl_get_supported_c > >> > >> r = -E2BIG; > >> if (nent>= cpuid->nent) > >> + goto out_free; > >> + > >> + /* Add support for Centaur's CPUID instruction. */ > >> + do_cpuid_ent(&cpuid_entries[nent], 0xC0000000, 0,&nent, > >> cpuid->nent); > > > nent overflow check missing here. Also, should probably skip if not a Via. > > If not a VIA, the "limit" will be "0", so the following cycle can not run. I think Intel defines CPUID to return the highest standard leaf, so it will be equivalent to cpuid(0x1a) or something like that. > Moreover, it seems that there is no method to know whther the CPU is a VIA or not in this function. Can't you check the vendor ID? see boot_cpu_data. > The nent overflow check is put after the cycle like the "0x8000000" case, and when on a VIA, the returned "limit" is not large (generally it is 0xC0000004), is it neccesary to add a more check here? Yes, otherwise userspace can supply a buffer that is exactly the wrong size and cause an overflow.
On 04/13/2011 02:05 PM, BrillyWu@viatech.com.cn wrote: > > >> > > >> + /* cpuid 0xC0000001.edx */ > > >> + const u32 kvm_supported_word5_x86_features = > > >> + F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | > > >> + F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | > > >> + F(PMM) | F(PMM_EN); > > >> + > > > > Are all of these features save wrt save/restore? (do they all act > > >on state in standard registers?) Do they need any control register > > >bits to be active or MSRs to configure? > > > These features depend on instructions for the PadLock hardware engine of VIA CPU. > > The PadLock instructions just act on standard registers like general X86 instructions, and the features have been enabled when the CPU leave the factory, so there is no need to activate any control register bits or configure MSRs. > I see there is a dependency on EFLAGS[30]. Does a VM entry clear this bit? If not, we have to do it ourselves. Yes, PadLock hardware engine has some association with EFLAGS[30], but it just required that the EFLAGS[30] should be set to "0" before using PadLock ACE instructions. It is recommanded that execute instruction sequence "pushf;popf" to clear this bit before using ACE instructions. AFAIK, the VM entry never sets the EFLAGS[30] bit, so it seems that we do not have to do it ourselves. > > >> @@ -2484,6 +2504,17 @@ static int kvm_dev_ioctl_get_supported_c > > >> > > >> r = -E2BIG; > > >> if (nent>= cpuid->nent) > > >> + goto out_free; > > >> + > > >> + /* Add support for Centaur's CPUID instruction. */ > > >> + do_cpuid_ent(&cpuid_entries[nent], 0xC0000000, 0,&nent, > > >> cpuid->nent); > > > > nent overflow check missing here. Also, should probably skip if not a Via. > > > If not a VIA, the "limit" will be "0", so the following cycle can not run. > I think Intel defines CPUID to return the highest standard leaf, so it will be equivalent to cpuid(0x1a) or something like that. Yes, you're right. > > Moreover, it seems that there is no method to know whther the CPU is a VIA or not in this function. > Can't you check the vendor ID? see boot_cpu_data. Good idea, thank you very much. > > The nent overflow check is put after the cycle like the "0x8000000" case, and when on a VIA, the returned "limit" is not large (generally it is 0xC0000004), is it neccesary to add a more check here? > Yes, otherwise userspace can supply a buffer that is exactly the wrong size and cause an overflow. OK, I will add the check. -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 04/14/2011 06:14 AM, BrillyWu@viatech.com.cn wrote: > On 04/13/2011 02:05 PM, BrillyWu@viatech.com.cn wrote: > > > >> > > > >> + /* cpuid 0xC0000001.edx */ > > > >> + const u32 kvm_supported_word5_x86_features = > > > >> + F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | > > > >> + F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | > > > >> + F(PMM) | F(PMM_EN); > > > >> + > > > > > > Are all of these features save wrt save/restore? (do they all act > > > >on state in standard registers?) Do they need any control register > > > >bits to be active or MSRs to configure? > > > > > These features depend on instructions for the PadLock hardware engine of VIA CPU. > > > The PadLock instructions just act on standard registers like general X86 instructions, and the features have been enabled when the CPU leave the factory, so there is no need to activate any control register bits or configure MSRs. > > > I see there is a dependency on EFLAGS[30]. Does a VM entry clear this bit? If not, we have to do it ourselves. > > Yes, PadLock hardware engine has some association with EFLAGS[30], but it just required that the EFLAGS[30] should be set to "0" > before using PadLock ACE instructions. It is recommanded that execute instruction sequence "pushf;popf" to clear this bit before using > ACE instructions. > AFAIK, the VM entry never sets the EFLAGS[30] bit, so it seems that we do not have to do it ourselves. I don't think we need to. kvm kernel code doesn't use padlock; other sources which might set EFLAGS[30] are: - the guest; but VMEXIT clears EFLAGS - userspace; but syscall/sysenter/int instructions clear EFLAGS[30] - another kernel thread; there is likely a popf in the context switch path somewhere (we should verify this)
> On 04/14/2011 06:14 AM, BrillyWu@viatech.com.cn wrote: > > On 04/13/2011 02:05 PM, BrillyWu@viatech.com.cn wrote: > > > > >> > > > > >> + /* cpuid 0xC0000001.edx */ > > > > >> + const u32 kvm_supported_word5_x86_features = > > > > >> + F(XSTORE) | F(XSTORE_EN) | > F(XCRYPT) | F(XCRYPT_EN) | > > > > >> + F(ACE2) | F(ACE2_EN) | F(PHE) | > F(PHE_EN) | > > > > >> + F(PMM) | F(PMM_EN); > > > > >> + > > > > > > > > Are all of these features save wrt save/restore? > (do they all act > > > > >on state in standard registers?) Do they need any control > > > register > >bits to be active or MSRs to configure? > > > > > > > These features depend on instructions for the PadLock > hardware engine of VIA CPU. > > > > The PadLock instructions just act on standard > registers like general X86 instructions, and the features have been > enabled when the CPU leave the factory, so there is no need to > activate any control register bits or configure MSRs. > > > > > I see there is a dependency on EFLAGS[30]. Does a VM > entry clear this bit? If not, we have to do it ourselves. > > > > Yes, PadLock hardware engine has some association with > EFLAGS[30], but it just required that the EFLAGS[30] should be set to > "0" > > before using PadLock ACE instructions. It is recommanded > that execute > > instruction sequence "pushf;popf" to clear this bit before > using ACE instructions. > > AFAIK, the VM entry never sets the EFLAGS[30] bit, so it > seems that we do not have to do it ourselves. > > I don't think we need to. kvm kernel code doesn't use padlock; other > sources which might set EFLAGS[30] are: > > - the guest; but VMEXIT clears EFLAGS > - userspace; but syscall/sysenter/int instructions clear EFLAGS[30] > - another kernel thread; there is likely a popf in the context switch > path somewhere (we should verify this) Thank you very much for telling me where the EFLAGS[30] might be set and cleared. In fact, adding the CPUID support into kvm kernel code is just to provide correct result for the calling of the "kvm_arch_get_supported_cpuid" function in Qemu-kvm application. There is no dependency on EFLAGS when calling VIA CPUID instruction. Before using padlock engine functions, the application first need detect is the features exist through cpuid instruction, then use ACE and other instructions such as PHE/RNG/PMM. And as previously said, only the ACE instructions required that the EFLAGS[30] should be set to "0", It is recommanded that execute instruction sequence "pushf;popf" to clear this bit before using ACE instructions. I have re-submitted this patch, please check it. Thanks! -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 04/14/2011 12:54 PM, BrillyWu@viatech.com.cn wrote: > > On 04/14/2011 06:14 AM, BrillyWu@viatech.com.cn wrote: > > > On 04/13/2011 02:05 PM, BrillyWu@viatech.com.cn wrote: > > > > > >> > > > > > >> + /* cpuid 0xC0000001.edx */ > > > > > >> + const u32 kvm_supported_word5_x86_features = > > > > > >> + F(XSTORE) | F(XSTORE_EN) | > > F(XCRYPT) | F(XCRYPT_EN) | > > > > > >> + F(ACE2) | F(ACE2_EN) | F(PHE) | > > F(PHE_EN) | > > > > > >> + F(PMM) | F(PMM_EN); > > > > > >> + > > > > > > > > > > Are all of these features save wrt save/restore? > > (do they all act > > > > > >on state in standard registers?) Do they need any control > > > > register> >bits to be active or MSRs to configure? > > > > > > > > > These features depend on instructions for the PadLock > > hardware engine of VIA CPU. > > > > > The PadLock instructions just act on standard > > registers like general X86 instructions, and the features have been > > enabled when the CPU leave the factory, so there is no need to > > activate any control register bits or configure MSRs. > > > > > > > I see there is a dependency on EFLAGS[30]. Does a VM > > entry clear this bit? If not, we have to do it ourselves. > > > > > > Yes, PadLock hardware engine has some association with > > EFLAGS[30], but it just required that the EFLAGS[30] should be set to > > "0" > > > before using PadLock ACE instructions. It is recommanded > > that execute > > > instruction sequence "pushf;popf" to clear this bit before > > using ACE instructions. > > > AFAIK, the VM entry never sets the EFLAGS[30] bit, so it > > seems that we do not have to do it ourselves. > > > > I don't think we need to. kvm kernel code doesn't use padlock; other > > sources which might set EFLAGS[30] are: > > > > - the guest; but VMEXIT clears EFLAGS > > - userspace; but syscall/sysenter/int instructions clear EFLAGS[30] > > - another kernel thread; there is likely a popf in the context switch > > path somewhere (we should verify this) > > Thank you very much for telling me where the EFLAGS[30] might > be set and cleared. > In fact, adding the CPUID support into kvm > kernel code is just to provide correct result for the calling of > the "kvm_arch_get_supported_cpuid" function in Qemu-kvm > application. That may not be sufficient for correct operation. Consider: - guest executes a padlock instruction - cpu sets EFLAGS[30] - external interrupt - VMEXIT (saves EFLAGS in GUEST_RFLAGS with EFLAGS[30] set) - external interrupt is processed, causes a task switch - EFLAGS[30] is cleared - some other process uses padlock instructions, which causes a reload of key information - switch back to kvm - VM entry (loads EFLAGS from GUEST_RFLAGS; still has EFLAGS[30] set) - guest executes following padlock instruction, doesn't reload key information so I think the code as is causes data corruption. > There is no dependency on EFLAGS when calling VIA CPUID > instruction. > > Before using padlock engine functions, the application first need detect > is the features exist through cpuid instruction, then use ACE and other > instructions such as PHE/RNG/PMM. > > And as previously said, only the ACE instructions required > that the EFLAGS[30] should be set to "0", It is recommanded > that execute instruction sequence "pushf;popf" to clear this bit > before using ACE instructions. The problem is that VM entry reloads eflags from saved state and is not affected by popf. > I have re-submitted this patch, please check it. Thanks! wrt cpuid it seems reasonable but that's we need to clear the EFLAGS[30] issue first.
--- a/arch/x86/kvm/x86.c 2011-04-12 10:16:07.713785938 +0800 +++ b/arch/x86/kvm/x86.c 2011-04-12 10:16:49.903786870 +0800 @@ -2331,6 +2331,12 @@ static void do_cpuid_ent(struct kvm_cpui F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) | 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM); + /* cpuid 0xC0000001.edx */ + const u32 kvm_supported_word5_x86_features = + F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | + F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | + F(PMM) | F(PMM_EN); + /* all calls to cpuid_count() should be made on the same cpu */ get_cpu(); do_cpuid_1_ent(entry, function, index); @@ -2440,6 +2446,20 @@ static void do_cpuid_ent(struct kvm_cpui entry->ecx &= kvm_supported_word6_x86_features; cpuid_mask(&entry->ecx, 6); break; + /*Add support for Centaur's CPUID instruction*/ + case 0xC0000000: + /*Just support up to 0xC0000004 now*/ + entry->eax = min(entry->eax, 0xC0000004); + break; + case 0xC0000001: + entry->edx &= kvm_supported_word5_x86_features; + cpuid_mask(&entry->edx, 5); + break; + case 0xC0000002: + case 0xC0000003: + case 0xC0000004: + /*Now nothing to do, reserved for the future*/ + break; } kvm_x86_ops->set_supported_cpuid(function, entry); @@ -2484,6 +2504,17 @@ static int kvm_dev_ioctl_get_supported_c r = -E2BIG; if (nent >= cpuid->nent) + goto out_free; + + /* Add support for Centaur's CPUID instruction. */ + do_cpuid_ent(&cpuid_entries[nent], 0xC0000000, 0, &nent, cpuid->nent); + limit = cpuid_entries[nent - 1].eax; + for (func = 0xC0000001; func <= limit && nent < cpuid->nent; ++func) + do_cpuid_ent(&cpuid_entries[nent], func, 0, + &nent, cpuid->nent); + + r = -E2BIG; + if (nent >= cpuid->nent) goto out_free;