From patchwork Fri Aug 25 16:53:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 9922515 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8C7696022E for ; Fri, 25 Aug 2017 16:54:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7731F2621D for ; Fri, 25 Aug 2017 16:54:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6BCC828401; Fri, 25 Aug 2017 16:54:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D16CB2621D for ; Fri, 25 Aug 2017 16:54:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754967AbdHYQxs (ORCPT ); Fri, 25 Aug 2017 12:53:48 -0400 Received: from mail-co1nam03on0088.outbound.protection.outlook.com ([104.47.40.88]:10944 "EHLO NAM03-CO1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754932AbdHYQxm (ORCPT ); Fri, 25 Aug 2017 12:53:42 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=EkxycguGkH7nR2yoH9R0v4cdYDB0Em7BEV+V70GmgJo=; b=cAollUQmLdZSfIrrmqC7QNNL+m66iQne1RGY/VfhCT2SST4ImefTh+kMsQKlXkubPVzqDRiHH0KwkRLkzxw8XmWKtHE+mzas5MICdV0gYd63AVF19GG29PyXrT85B15E+7LfGzVX0l29wsBg3GUbB3l3+2nx4fItaAlmezlfMqg= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=brijesh.singh@amd.com; Received: from [10.236.136.62] (165.204.77.1) by SN1PR12MB0158.namprd12.prod.outlook.com (10.162.3.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.1385.9; Fri, 25 Aug 2017 16:53:36 +0000 Cc: brijesh.singh@amd.com, Linux-Next Mailing List , Linux Kernel Mailing List , Yu Zhang , paolo.bonzini@gmail.com Subject: Re: linux-next: manual merge of the kvm tree with the tip tree To: Tom Lendacky , Paolo Bonzini , Stephen Rothwell , =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , KVM , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Peter Zijlstra References: <20170825143930.494744fe@canb.auug.org.au> <2984689e-ab4e-0c22-7151-adfeeffce4ed@redhat.com> From: Brijesh Singh Message-ID: Date: Fri, 25 Aug 2017 11:53:32 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: BN6PR08CA0086.namprd08.prod.outlook.com (10.172.143.152) To SN1PR12MB0158.namprd12.prod.outlook.com (10.162.3.145) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3ab7c5d8-d260-4329-184a-08d4ebd9d4ec X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(2017030254152)(300000503095)(300135400095)(48565401081)(201703131423075)(201703031133081)(201702281549075)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095); SRVR:SN1PR12MB0158; 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Applying >> a mask based on properties of the host MMU is incorrect. >> >> Second, the masks computed by __reset_rsvds_bits_mask also apply to >> guest page tables, where the C bit is reserved since we don't emulate >> SME. >> >> Something like this: > Thanks for the tip, I have expanded the patch to cover tdp cases and have verified that it works fine with SME enabled KVM. If you are okay with this then I can send patch. > Thanks Paolo, Brijesh and I will test this and make sure everything works > properly with this patch. > > Thanks, > Tom > >> >> diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c >> index 2dafd36368cc..e0597d703d72 100644 >> --- a/arch/x86/kvm/mmu.c >> +++ b/arch/x86/kvm/mmu.c >> @@ -4142,16 +4142,24 @@ void >> reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context) >> { >> bool uses_nx = context->nx || context->base_role.smep_andnot_wp; >> + struct rsvd_bits_validate *shadow_zero_check; >> + int i; >> /* >> * Passing "true" to the last argument is okay; it adds a check >> * on bit 8 of the SPTEs which KVM doesn't use anyway. >> */ >> - __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check, >> + shadow_zero_check = &context->shadow_zero_check; >> + __reset_rsvds_bits_mask(vcpu, shadow_zero_check, >> boot_cpu_data.x86_phys_bits, >> context->shadow_root_level, uses_nx, >> guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES), >> is_pse(vcpu), true); >> + >> + for (i = context->shadow_root_level; --i >= 0; ) { >> + shadow_zero_check->rsvd_bits_mask[i][0] &= ~shadow_me_mask; >> + shadow_zero_check->rsvd_bits_mask[i][1] &= ~shadow_me_mask; >> + } >> } >> EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask); >> >> Can you please fix it up? Please Cc me at paolo.bonzini@gmail.com too >> because I'll be on vacation next week. >> >> (And thanks Stephen for the heads-up!) >> >> Paolo >> Acked-by: Paolo Bonzini diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index ccb70b8..7a8edc0 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -4109,16 +4109,30 @@ void reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context) { bool uses_nx = context->nx || context->base_role.smep_andnot_wp; + struct rsvd_bits_validate *shadow_zero_check; + int i; /* diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index ccb70b8..7a8edc0 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -4109,16 +4109,30 @@ void reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context) { bool uses_nx = context->nx || context->base_role.smep_andnot_wp; + struct rsvd_bits_validate *shadow_zero_check; + int i; /* * Passing "true" to the last argument is okay; it adds a check * on bit 8 of the SPTEs which KVM doesn't use anyway. */ - __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check, + shadow_zero_check = &context->shadow_zero_check; + __reset_rsvds_bits_mask(vcpu, shadow_zero_check, boot_cpu_data.x86_phys_bits, context->shadow_root_level, uses_nx, guest_cpuid_has_gbpages(vcpu), is_pse(vcpu), true); + + if (!shadow_me_mask) + return; + + for (i = context->shadow_root_level; --i >= 0;) { + shadow_zero_check->rsvd_bits_mask[i][0] &= ~shadow_me_mask; + shadow_zero_check->rsvd_bits_mask[i][1] &= ~shadow_me_mask; + shadow_zero_check->rsvd_bits_mask[i][2] &= ~shadow_me_mask; + shadow_zero_check->rsvd_bits_mask[i][3] &= ~shadow_me_mask; + } + } EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask); @@ -4136,8 +4150,13 @@ static void reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context) { + struct rsvd_bits_validate *shadow_zero_check; + int i; + + shadow_zero_check = &context->shadow_zero_check; + if (boot_cpu_is_amd()) - __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check, + __reset_rsvds_bits_mask(vcpu, shadow_zero_check, boot_cpu_data.x86_phys_bits, context->shadow_root_level, false, boot_cpu_has(X86_FEATURE_GBPAGES), @@ -4147,6 +4166,15 @@ reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, boot_cpu_data.x86_phys_bits, false); + if (!shadow_me_mask) + return; + + for (i = context->shadow_root_level; --i >= 0;) { + shadow_zero_check->rsvd_bits_mask[i][0] &= ~shadow_me_mask; + shadow_zero_check->rsvd_bits_mask[i][1] &= ~shadow_me_mask; + shadow_zero_check->rsvd_bits_mask[i][2] &= ~shadow_me_mask; + shadow_zero_check->rsvd_bits_mask[i][3] &= ~shadow_me_mask; + } } /* diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h index 3cc7255..d7d248a 100644 --- a/arch/x86/kvm/mmu.h +++ b/arch/x86/kvm/mmu.h @@ -48,7 +48,7 @@ static inline u64 rsvd_bits(int s, int e) { - return __sme_clr(((1ULL << (e - s + 1)) - 1) << s); + return ((1ULL << (e - s + 1)) - 1) << s; } void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask, u64 mmio_value);