From patchwork Mon Jan 22 23:53:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 13526495 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8F4364CDE; Mon, 22 Jan 2024 23:55:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705967752; cv=none; b=QjJw5PFtj65c7xwLrb5Af+FaXCIZjz9M1VapA49XK2MZ6CVW72jCdMUhRW8HqdqyNPTadu9bfb1cjwH9F2F3rOL/mH3SGV11b/gPE2loBjvrCQ02w7UXTrD4yX3q7cxA3nsKtCZu5bWMqJSSOxNCoswZct7fAsAorkwhfrgSRT4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705967752; c=relaxed/simple; bh=l5OSF5BW6i68hDmdAYtfztFn1BeBC/ZkQJ3rYLau+Ig=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ajD72uId1ekwlVyi0o20NmtgBJ/PzkSstSBNb8OByVzbkul0+sSymC4hNFTCSkyBWoMgmGbo+/QrViA4vaUMSw4vcJ+xAAn59H4y8iPNP5iEQERCXdI8UjTkDM8LoQbEC1f5prffH26sQSaG975rF3nfGU6frq91Df4ioRlELWo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ai5cavth; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ai5cavth" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1705967751; x=1737503751; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=l5OSF5BW6i68hDmdAYtfztFn1BeBC/ZkQJ3rYLau+Ig=; b=ai5cavthuvdImaDsfK5AHY0ve/GltiqRUjnj5TarMXacIUJRaJFTlLWi cmqFdfJm29Zi7VdEyOeNAJ53RBqR39cU3zJn/0w2xxyINdZMYvbujYUVk 5BLwYjH4XeQdQ6xd+TJ5dYx/H/Llvu+LyBYS1Wffj9v59qagoUwoHlWe4 jDg6DprlweyXKU+GGHhmRsftrGb9AVAHemxlXH2kWzhJkZVw1HJz0NAE1 RNMQVxciWvD4x6502JJBSwAvNWcgWYiGUwSHQXgLEa+zLHjJF4dxo2oEl bbEy8U+wxQfiGX4ny2cHZe3svaaCrPSRvq7TF5b1y04XM+ZgQ1PXXyoDa g==; X-IronPort-AV: E=McAfee;i="6600,9927,10961"; a="8016447" X-IronPort-AV: E=Sophos;i="6.05,212,1701158400"; d="scan'208";a="8016447" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2024 15:55:36 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,212,1701158400"; d="scan'208";a="1468189" Received: from ls.sc.intel.com (HELO localhost) ([172.25.112.31]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2024 15:55:35 -0800 From: isaku.yamahata@intel.com To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, Paolo Bonzini , erdemaktas@google.com, Sean Christopherson , Sagi Shahar , Kai Huang , chen.bo@intel.com, hang.yuan@intel.com, tina.zhang@intel.com Subject: [PATCH v18 059/121] KVM: TDX: Require TDP MMU and mmio caching for TDX Date: Mon, 22 Jan 2024 15:53:35 -0800 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Isaku Yamahata As TDP MMU is becoming main stream than the legacy MMU, the legacy MMU support for TDX isn't implemented. TDX requires KVM mmio caching. Disable TDX support when TDP MMU or mmio caching aren't supported. Signed-off-by: Isaku Yamahata --- arch/x86/kvm/mmu/mmu.c | 1 + arch/x86/kvm/vmx/main.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index f338b85d6d5b..7db152f46d82 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -104,6 +104,7 @@ module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644); * If the hardware supports that we don't need to do shadow paging. */ bool tdp_enabled = false; +EXPORT_SYMBOL_GPL(tdp_enabled); static bool __ro_after_init tdp_mmu_allowed; diff --git a/arch/x86/kvm/vmx/main.c b/arch/x86/kvm/vmx/main.c index f55ac09edc60..e77c045dca84 100644 --- a/arch/x86/kvm/vmx/main.c +++ b/arch/x86/kvm/vmx/main.c @@ -62,6 +62,17 @@ static __init int vt_hardware_setup(void) if (enable_ept) kvm_mmu_set_ept_masks(enable_ept_ad_bits, cpu_has_vmx_ept_execute_only()); + /* TDX requires KVM TDP MMU. */ + if (enable_tdx && !tdp_enabled) { + enable_tdx = false; + pr_warn_ratelimited("TDX requires TDP MMU. Please enable TDP MMU for TDX.\n"); + } + + /* TDX requires MMIO caching. */ + if (enable_tdx && !enable_mmio_caching) { + enable_tdx = false; + pr_warn_ratelimited("TDX requires mmio caching. Please enable mmio caching for TDX.\n"); + } enable_tdx = enable_tdx && !tdx_hardware_setup(&vt_x86_ops);