From patchwork Wed Sep 2 08:09:46 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavel Fedin X-Patchwork-Id: 7109521 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C4C99BEEC1 for ; Wed, 2 Sep 2015 08:10:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 04EBA20644 for ; Wed, 2 Sep 2015 08:10:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8D5BC202A1 for ; Wed, 2 Sep 2015 08:10:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753303AbbIBIKF (ORCPT ); Wed, 2 Sep 2015 04:10:05 -0400 Received: from mailout4.w1.samsung.com ([210.118.77.14]:8798 "EHLO mailout4.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753197AbbIBIJ5 (ORCPT ); Wed, 2 Sep 2015 04:09:57 -0400 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout4.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NU100CG3IOI9470@mailout4.w1.samsung.com> for kvm@vger.kernel.org; Wed, 02 Sep 2015 09:09:54 +0100 (BST) X-AuditID: cbfec7f5-f794b6d000001495-4c-55e6aed2db40 Received: from eusync2.samsung.com ( [203.254.199.212]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id 1A.19.05269.2DEA6E55; Wed, 2 Sep 2015 09:09:54 +0100 (BST) Received: from fedinw7x64.rnd.samsung.ru ([106.109.131.169]) by eusync2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NU100D5JIOD5Z00@eusync2.samsung.com>; Wed, 02 Sep 2015 09:09:54 +0100 (BST) From: Pavel Fedin To: kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Cc: Marc Zyngier , Christoffer Dall , Andre Przywara Subject: [PATCH v2 2/5] KVM: arm64: Implement vGICv3 distributor and redistributor access from userspace Date: Wed, 02 Sep 2015 11:09:46 +0300 Message-id: X-Mailer: git-send-email 2.4.4 In-reply-to: References: In-reply-to: References: X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprLLMWRmVeSWpSXmKPExsVy+t/xK7qX1j0LNVizQdZixbyfjBYvXv9j tJgztdDi46nj7BZ/7/xjc2D1WDNvDaPHnWt72DzOb1rD7PF5k1wASxSXTUpqTmZZapG+XQJX xs/n71kK3tpVtLxczNLAeNuwi5GTQ0LAROLNtFfsELaYxIV769m6GLk4hASWMkr0n1oK5bQx SXS8WMcMUsUmoC5x+usHFhBbRMBU4vm/t6wgRcwCLYwS8/YcBSsSFsiSaOnfygpiswioSlw9 uBqsgVcgWmLhrLlsEOvkJK5cnw5mcwqYS2w/dIUJxBYSMJP41D+DGZf4BEb+BYwMqxhFU0uT C4qT0nON9IoTc4tL89L1kvNzNzFCAu3rDsalx6wOMQpwMCrx8DYkPgsVYk0sK67MPcQowcGs JMLLowsU4k1JrKxKLcqPLyrNSS0+xCjNwaIkzjtz1/sQIYH0xJLU7NTUgtQimCwTB6dUA+OZ 69PErYvW/ypK9vwl/n7lp2d7n59cK8aVHnr8psavKe+iC1YVryvc9kPa3iiQRznDe/eZrvfZ 7VZrhYJNNZs2HuC1WnLiiDeveffbnGvWGRsV/p84I9wf/TI/Tm3HjndRBR9//crzmpmz5veS 7z/e/1RMOzrZ1v2ux09WlYet86982WMVaL1EiaU4I9FQi7moOBEAJnbQQjACAAA= Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The access is done similar to vGICv2, using KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_REDIST_REGS with KVM_SET_DEVICE_ATTR and KVM_GET_DEVICE_ATTR ioctls. Some registers are 64-bit wide according to the specification. KVM_DEV_ARM_VGIC_64BIT flag is introduced, allowing to perform full 64-bit accesses. Signed-off-by: Pavel Fedin --- Documentation/virtual/kvm/devices/arm-vgic.txt | 34 ++++++++- arch/arm64/include/uapi/asm/kvm.h | 2 + virt/kvm/arm/vgic-v3-emul.c | 96 ++++++++++++++++++++++---- 3 files changed, 115 insertions(+), 17 deletions(-) diff --git a/Documentation/virtual/kvm/devices/arm-vgic.txt b/Documentation/virtual/kvm/devices/arm-vgic.txt index 3fb9054..43f2627 100644 --- a/Documentation/virtual/kvm/devices/arm-vgic.txt +++ b/Documentation/virtual/kvm/devices/arm-vgic.txt @@ -43,10 +43,13 @@ Groups: KVM_DEV_ARM_VGIC_GRP_DIST_REGS Attributes: The attr field of kvm_device_attr encodes two values: - bits: | 63 .... 40 | 39 .. 32 | 31 .... 0 | - values: | reserved | cpu id | offset | + bits: | 63 | 62 .. 40 | 39 .. 32 | 31 .... 0 | + values: | size | reserved | cpu id | offset | All distributor regs are (rw, 32-bit) + For GICv3 some regs are also (rw, 64-bit) according to the specification. + In order to perform full 64-bit access 'size' bit should be set to 1. + KVM_DEV_ARM_VGIC_64BIT flag value is provided for this purpose. The offset is relative to the "Distributor base address" as defined in the GICv2 specs. Getting or setting such a register has the same effect as @@ -54,9 +57,34 @@ Groups: specified with cpu id field. Note that most distributor fields are not banked, but return the same value regardless of the cpu id used to access the register. + + Limitations: + - Priorities are not implemented, and registers are RAZ/WI + Errors: + -ENODEV: Getting or setting this register is not yet supported + -EBUSY: One or more VCPUs are running + + KVM_DEV_ARM_VGIC_GRP_REDIST_REGS + Attributes: + The attr field of kvm_device_attr encodes two values: + bits: | 63 | 62 .. 40 | 39 .. 32 | 31 .... 0 | + values: | size | reserved | cpu id | offset | + + All redistributor regs are (rw, 32-bit) + For GICv3 some regs are also (rw, 64-bit) according to the specification. + In order to perform full 64-bit access 'size' bit should be set to 1. + KVM_DEV_ARM_VGIC_64BIT flag value is provided for this purpose. + + + The offset is relative to the "Redistributor base address" as defined in + the GICv3 specs. Getting or setting such a register has the same effect as + reading or writing the register on the actual hardware from the cpu + specified with cpu id field. Note that most distributor fields are not + banked, but return the same value regardless of the cpu id used to access + the register. + Limitations: - Priorities are not implemented, and registers are RAZ/WI - - Currently only implemented for KVM_DEV_TYPE_ARM_VGIC_V2. Errors: -ENODEV: Getting or setting this register is not yet supported -EBUSY: One or more VCPUs are running diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h index 0cd7b59..b7a0a6d 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -196,6 +196,7 @@ struct kvm_arch_memory_slot { #define KVM_DEV_ARM_VGIC_GRP_ADDR 0 #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1 #define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2 +#define KVM_DEV_ARM_VGIC_64BIT (1ULL << 63) #define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32 #define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT) #define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0 @@ -203,6 +204,7 @@ struct kvm_arch_memory_slot { #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3 #define KVM_DEV_ARM_VGIC_GRP_CTRL 4 #define KVM_DEV_ARM_VGIC_CTRL_INIT 0 +#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5 /* KVM_IRQ_LINE irq field index values */ #define KVM_ARM_IRQ_TYPE_SHIFT 24 diff --git a/virt/kvm/arm/vgic-v3-emul.c b/virt/kvm/arm/vgic-v3-emul.c index e661e7f..66d2b54 100644 --- a/virt/kvm/arm/vgic-v3-emul.c +++ b/virt/kvm/arm/vgic-v3-emul.c @@ -39,6 +39,7 @@ #include #include #include +#include #include #include @@ -990,6 +991,78 @@ void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg) vgic_kick_vcpus(vcpu->kvm); } +static int vgic_v3_attr_regs_access(struct kvm_device *dev, + struct kvm_device_attr *attr, + bool is_write) +{ + const struct vgic_io_range *ranges; + phys_addr_t offset; + int cpuid, ret; + struct vgic_dist *vgic = &dev->kvm->arch.vgic; + struct kvm_exit_mmio mmio; + + cpuid = (attr->attr & KVM_DEV_ARM_VGIC_CPUID_MASK) >> + KVM_DEV_ARM_VGIC_CPUID_SHIFT; + + switch (attr->group) { + case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: + offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; + mmio.phys_addr = vgic->vgic_dist_base; + ranges = vgic_v3_dist_ranges; + break; + case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS: + offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; + mmio.phys_addr = vgic->vgic_redist_base; + ranges = vgic_redist_ranges; + break; + default: + return -ENXIO; + } + + mmio.is_write = is_write; + + if (attr->attr & KVM_DEV_ARM_VGIC_64BIT) + { + u64 __user *uaddr = (u64 __user *)(long)attr->addr; + __le64 data; + + if (is_write) { + u64 reg; + + if (get_user(reg, uaddr)) + return -EFAULT; + data = cpu_to_le64(reg); + } + + mmio.data = &data; + ret = vgic_attr_regs_access(dev, ranges, &mmio, offset, + sizeof(data), cpuid); + + if (!ret && !is_write) + ret = put_user(le64_to_cpu(data), uaddr); + } else { + u32 __user *uaddr = (u32 __user *)(long)attr->addr; + __le32 data; + + if (is_write) { + u32 reg; + + if (get_user(reg, uaddr)) + return -EFAULT; + data = cpu_to_le32(reg); + } + + mmio.data = &data; + ret = vgic_attr_regs_access(dev, ranges, &mmio, offset, + sizeof(data), cpuid); + + if (!ret && !is_write) + ret = put_user(le32_to_cpu(data), uaddr); + } + + return ret; +} + static int vgic_v3_create(struct kvm_device *dev, u32 type) { return kvm_vgic_create(dev->kvm, type); @@ -1009,13 +1082,7 @@ static int vgic_v3_set_attr(struct kvm_device *dev, if (ret != -ENXIO) return ret; - switch (attr->group) { - case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: - case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: - return -ENXIO; - } - - return -ENXIO; + return vgic_v3_attr_regs_access(dev, attr, true); } static int vgic_v3_get_attr(struct kvm_device *dev, @@ -1027,18 +1094,14 @@ static int vgic_v3_get_attr(struct kvm_device *dev, if (ret != -ENXIO) return ret; - switch (attr->group) { - case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: - case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: - return -ENXIO; - } - - return -ENXIO; + return vgic_v3_attr_regs_access(dev, attr, false); } static int vgic_v3_has_attr(struct kvm_device *dev, struct kvm_device_attr *attr) { + phys_addr_t offset; + switch (attr->group) { case KVM_DEV_ARM_VGIC_GRP_ADDR: switch (attr->attr) { @@ -1051,6 +1114,11 @@ static int vgic_v3_has_attr(struct kvm_device *dev, } break; case KVM_DEV_ARM_VGIC_GRP_DIST_REGS: + offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; + return vgic_has_attr_regs(vgic_v3_dist_ranges, offset); + case KVM_DEV_ARM_VGIC_GRP_REDIST_REGS: + offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK; + return vgic_has_attr_regs(vgic_redist_ranges, offset); case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: return -ENXIO; case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: