From patchwork Mon Jan 22 23:53:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 13526487 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86DF8627E4; Mon, 22 Jan 2024 23:55:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705967748; cv=none; b=AaT0BB3Y+5VqFXEkG4iZFvs/NZj95v2yfQV6OBOXvg7nd51IYQ+c2XO68CHpeVVtS4PXX/LUvyk/R+LTRHmosdRPVnsf1NsMY2NmgECLEOwUrem9PjQPH+KMXrgSZqLE3gw5uTxbsv6c2ZTvHSsSiECivKN+0UJTicfpb7RZMRI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705967748; c=relaxed/simple; bh=l6Zco0SEeOUpI7QVkUZQZzcUgZZfpXd/uMYRqYQK7PQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=laV+fVmXNHBX+oBdy82ILKELSSZ0N80b+XfG3EEoOH2ED/KEi04TDTjwZ0GqMABQExBLELC37qODRbfZA5HVnozPmeS6ajOomuUKeV2AKEngoo7K1X2uZ+kInXfTwrGpQ/xSA0u6p8GzD0d9PyrtbCkBpoV966f3aneItH+Sqgw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=leVZauRd; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="leVZauRd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1705967747; x=1737503747; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=l6Zco0SEeOUpI7QVkUZQZzcUgZZfpXd/uMYRqYQK7PQ=; b=leVZauRdJxPa39RipDY4+M9SVESTN+HTSzZa6URMBIPBjD2P3xUie5MF +zAjClV860JV6p4/TGMNhfDoFO1T2lGm6LOEYNc7WGHQpJophffc/YS0H 8WY1YDStEkfH4rGhxPgj4i6pEoNBclODI6shF6EYhmFDc7aDJGlARnJGr UYd344goJADTc2BFPuoHofN66ZRe0za/VG2YFAZyDepTRR8nIhFmBM4Eh UgpHdYSS7ehLa3LF1p23EN/nBwjHEbMmNyUJpgYj4DDeEXIngUbTF2imb K2p7jjFJcYYT58QkxLuX6SzcH/kFcK1dZXaZ6bLuknUaJKXowMMJe7yZi w==; X-IronPort-AV: E=McAfee;i="6600,9927,10961"; a="8016416" X-IronPort-AV: E=Sophos;i="6.05,212,1701158400"; d="scan'208";a="8016416" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2024 15:55:36 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,212,1701158400"; d="scan'208";a="1468164" Received: from ls.sc.intel.com (HELO localhost) ([172.25.112.31]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2024 15:55:33 -0800 From: isaku.yamahata@intel.com To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, Paolo Bonzini , erdemaktas@google.com, Sean Christopherson , Sagi Shahar , Kai Huang , chen.bo@intel.com, hang.yuan@intel.com, tina.zhang@intel.com, Sean Christopherson Subject: [PATCH v18 055/121] KVM: VMX: Move setting of EPT MMU masks to common VT-x code Date: Mon, 22 Jan 2024 15:53:31 -0800 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Sean Christopherson EPT MMU masks are used commonly for VMX and TDX. The value needs to be initialized in common code before both VMX/TDX-specific initialization code. Signed-off-by: Sean Christopherson Signed-off-by: Isaku Yamahata --- arch/x86/kvm/vmx/main.c | 9 +++++++++ arch/x86/kvm/vmx/vmx.c | 4 ---- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/vmx/main.c b/arch/x86/kvm/vmx/main.c index de4b6f924a36..8059b44ed159 100644 --- a/arch/x86/kvm/vmx/main.c +++ b/arch/x86/kvm/vmx/main.c @@ -4,6 +4,7 @@ #include "x86_ops.h" #include "vmx.h" #include "nested.h" +#include "mmu.h" #include "pmu.h" #include "tdx.h" #include "tdx_arch.h" @@ -54,6 +55,14 @@ static __init int vt_hardware_setup(void) if (ret) return ret; + /* + * As kvm_mmu_set_ept_masks() updates enable_mmio_caching, call it + * before checking enable_mmio_caching. + */ + if (enable_ept) + kvm_mmu_set_ept_masks(enable_ept_ad_bits, + cpu_has_vmx_ept_execute_only()); + enable_tdx = enable_tdx && !tdx_hardware_setup(&vt_x86_ops); return 0; diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 185e22a2e101..c2da39ceb02b 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -8452,10 +8452,6 @@ __init int vmx_hardware_setup(void) set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ - if (enable_ept) - kvm_mmu_set_ept_masks(enable_ept_ad_bits, - cpu_has_vmx_ept_execute_only()); - /* * Setup shadow_me_value/shadow_me_mask to include MKTME KeyID * bits to shadow_zero_check.