From patchwork Mon Oct 16 16:14:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 13423661 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D90FCCDB482 for ; Mon, 16 Oct 2023 16:17:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234076AbjJPQRq (ORCPT ); Mon, 16 Oct 2023 12:17:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234071AbjJPQRZ (ORCPT ); Mon, 16 Oct 2023 12:17:25 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 17BC8D5A; Mon, 16 Oct 2023 09:17:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1697473022; x=1729009022; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8T6zLvlaAzAFwyaBg/0GChxfVbg0Fq6wwYkBsoq3oNs=; b=GRk8xEnOD4ru75vCy2o4PoRnfi4pty9s76wxZRUhRPDIhfjKjhJib//N lc0rzgkeDZq91aH+Jh2Njy0dLVc2zS8269r/DHN9XW6QJeB16uR6ZhriH KBQ4HHEJQlLjoDXd7nZV/Fan4CM6coFdbp+aG4/tWINsyICYPWCtTSYcw bpUxxU3UGny+h0oDNuxMepwiIkssmG5B+f7lnUFg84Ruh6u4MhAX6iQ03 V73SDS1pFKz+h/FMdoNStbYkzTWQv2ciJmKJMApcg3yxemW15q2uTyqAG HDPHHsV2bqwrVbqC/SB2wmlA0VjpD/09STb6WGF1DMOR9LszKBZ0GJBEs w==; X-IronPort-AV: E=McAfee;i="6600,9927,10865"; a="364921814" X-IronPort-AV: E=Sophos;i="6.03,229,1694761200"; d="scan'208";a="364921814" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2023 09:15:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10865"; a="846448144" X-IronPort-AV: E=Sophos;i="6.03,229,1694761200"; d="scan'208";a="846448144" Received: from ls.sc.intel.com (HELO localhost) ([172.25.112.31]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2023 09:15:46 -0700 From: isaku.yamahata@intel.com To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, Paolo Bonzini , erdemaktas@google.com, Sean Christopherson , Sagi Shahar , David Matlack , Kai Huang , Zhi Wang , chen.bo@intel.com, hang.yuan@intel.com, tina.zhang@intel.com Subject: [PATCH v16 054/116] KVM: TDX: Require TDP MMU and mmio caching for TDX Date: Mon, 16 Oct 2023 09:14:06 -0700 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Isaku Yamahata As TDP MMU is becoming main stream than the legacy MMU, the legacy MMU support for TDX isn't implemented. TDX requires KVM mmio caching. Disable TDX support when TDP MMU or mmio caching aren't supported. Signed-off-by: Isaku Yamahata --- arch/x86/kvm/mmu/mmu.c | 1 + arch/x86/kvm/vmx/main.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index e1f42fdcd248..91250b2a7081 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -104,6 +104,7 @@ module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644); * If the hardware supports that we don't need to do shadow paging. */ bool tdp_enabled = false; +EXPORT_SYMBOL_GPL(tdp_enabled); static bool __ro_after_init tdp_mmu_allowed; diff --git a/arch/x86/kvm/vmx/main.c b/arch/x86/kvm/vmx/main.c index 17d119f3c4a8..fda13fd37cae 100644 --- a/arch/x86/kvm/vmx/main.c +++ b/arch/x86/kvm/vmx/main.c @@ -58,6 +58,17 @@ static __init int vt_hardware_setup(void) if (enable_ept) kvm_mmu_set_ept_masks(enable_ept_ad_bits, cpu_has_vmx_ept_execute_only()); + /* TDX requires KVM TDP MMU. */ + if (enable_tdx && !tdp_enabled) { + enable_tdx = false; + pr_warn_ratelimited("TDX requires TDP MMU. Please enable TDP MMU for TDX.\n"); + } + + /* TDX requires MMIO caching. */ + if (enable_tdx && !enable_mmio_caching) { + enable_tdx = false; + pr_warn_ratelimited("TDX requires mmio caching. Please enable mmio caching for TDX.\n"); + } enable_tdx = enable_tdx && !tdx_hardware_setup(&vt_x86_ops);