From patchwork Tue Nov 7 14:56:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 13448982 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6059131A64 for ; Tue, 7 Nov 2023 15:01:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="GZEoeGY9" Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EDFCF30E1; Tue, 7 Nov 2023 06:59:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699369141; x=1730905141; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nDz5ZFHsySJuVF9S9JoOemj38IFxKvmeZ5aZEy093Fo=; b=GZEoeGY9xWQ8XVp68uOiQUOvJoDDEMvaJDFoGXK8EhEU63Kf/vJWnu3T R6KYONbI9a5PE7cG4USfTScjVf3AV/1VywGAJFOdojrrHBSDpD0vz5B/B iaNgByCDC0Jfn17bbNC2DN4qImY8mXAvVA7Kby5X9rqhEgWnhfIV90jr8 +m7/x/2SCUT/AIyYa6ylMivoPdMPhiHmnIWQ/BUICHdJOpLssyaMlftEt OtdRb3/Sj1dyJ21qjGoucLrxVyKq9L4KpWdXg6059D+E7uK8728KmHdTM K9CPvZrvtnNmhsCOKdm34l0D3cfkhoxugGZpf1owzR4xIT49kxuZrKRoR Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10887"; a="2462332" X-IronPort-AV: E=Sophos;i="6.03,284,1694761200"; d="scan'208";a="2462332" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2023 06:58:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,284,1694761200"; d="scan'208";a="10851397" Received: from ls.sc.intel.com (HELO localhost) ([172.25.112.31]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2023 06:58:12 -0800 From: isaku.yamahata@intel.com To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, Paolo Bonzini , erdemaktas@google.com, Sean Christopherson , Sagi Shahar , David Matlack , Kai Huang , Zhi Wang , chen.bo@intel.com, hang.yuan@intel.com, tina.zhang@intel.com, Sean Christopherson Subject: [PATCH v17 050/116] KVM: VMX: Move setting of EPT MMU masks to common VT-x code Date: Tue, 7 Nov 2023 06:56:16 -0800 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Sean Christopherson EPT MMU masks are used commonly for VMX and TDX. The value needs to be initialized in common code before both VMX/TDX-specific initialization code. Signed-off-by: Sean Christopherson Signed-off-by: Isaku Yamahata --- arch/x86/kvm/vmx/main.c | 9 +++++++++ arch/x86/kvm/vmx/vmx.c | 4 ---- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/vmx/main.c b/arch/x86/kvm/vmx/main.c index e5a918d81200..0180b3e5b1f8 100644 --- a/arch/x86/kvm/vmx/main.c +++ b/arch/x86/kvm/vmx/main.c @@ -4,6 +4,7 @@ #include "x86_ops.h" #include "vmx.h" #include "nested.h" +#include "mmu.h" #include "pmu.h" #include "tdx.h" #include "tdx_arch.h" @@ -50,6 +51,14 @@ static __init int vt_hardware_setup(void) if (ret) return ret; + /* + * As kvm_mmu_set_ept_masks() updates enable_mmio_caching, call it + * before checking enable_mmio_caching. + */ + if (enable_ept) + kvm_mmu_set_ept_masks(enable_ept_ad_bits, + cpu_has_vmx_ept_execute_only()); + enable_tdx = enable_tdx && !tdx_hardware_setup(&vt_x86_ops); return 0; diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index af31ad8e893b..2dd0fe161d27 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -8409,10 +8409,6 @@ __init int vmx_hardware_setup(void) set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ - if (enable_ept) - kvm_mmu_set_ept_masks(enable_ept_ad_bits, - cpu_has_vmx_ept_execute_only()); - /* * Setup shadow_me_value/shadow_me_mask to include MKTME KeyID * bits to shadow_zero_check.