From patchwork Fri Mar 13 10:53:02 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Kohl X-Patchwork-Id: 11695 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n2DArMnQ008741 for ; Fri, 13 Mar 2009 10:53:22 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758084AbZCMKxW (ORCPT ); Fri, 13 Mar 2009 06:53:22 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1757813AbZCMKxV (ORCPT ); Fri, 13 Mar 2009 06:53:21 -0400 Received: from main.gmane.org ([80.91.229.2]:52736 "EHLO ciao.gmane.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756435AbZCMKxU (ORCPT ); Fri, 13 Mar 2009 06:53:20 -0400 Received: from list by ciao.gmane.org with local (Exim 4.43) id 1Li50w-0006Wk-DR for kvm@vger.kernel.org; Fri, 13 Mar 2009 10:53:18 +0000 Received: from 192.100.130.229 ([192.100.130.229]) by main.gmane.org with esmtp (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Fri, 13 Mar 2009 10:53:18 +0000 Received: from bernhard.kohl by 192.100.130.229 with local (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Fri, 13 Mar 2009 10:53:18 +0000 X-Injected-Via-Gmane: http://gmane.org/ To: kvm@vger.kernel.org From: Bernhard Kohl Subject: [PATCH] KVM: IOAPIC: Do not check polarity Date: Fri, 13 Mar 2009 10:53:02 +0000 (UTC) Lines: 41 Message-ID: Mime-Version: 1.0 X-Complaints-To: usenet@ger.gmane.org X-Gmane-NNTP-Posting-Host: main.gmane.org User-Agent: Loom/3.14 (http://gmane.org/) X-Loom-IP: 192.100.130.229 (Mozilla/5.0 (X11; U; Linux i686; de; rv:1.9.0.7) Gecko/2009030503 Fedora/3.0.7-1.fc10 Firefox/3.0.7) Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org NSN's proprietary OS DMX heavily depends on a correct BIOS MP table. From there it also gets the information for initialization of PCI devices. We defined the polarity and trigger mode as for standard PCI devices "low level". The OS programs the ioapic the same way. Nothing else in QEMU's and KVM's IRQ, PIC, IOAPIC and LAPIC code cares about interrupt polarity. The "level" is always used as a logical value. So we must not change the level here. If we do so, PCI low level interrupts are not fired if the guest raises the interrupt (level=1), but first if it is reset again (level=0). This can result in infinite waiting for a single interupt. For example the DMX guest waits for the link up interupt of the E1000 ethernet device before enabling the TX and RX interupts of this device. E1000 emulation sets level=1, no interrupt is fired, deadlock. This does not happen if we use the -no-kvm-irqchip option. This means that qemu's ioapic does not care about the polarity and kvm's ioapic shouldn't do either. Signed-off-by: Bernhard Kohl --- virt/kvm/ioapic.c | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) else { diff --git a/virt/kvm/ioapic.c b/virt/kvm/ioapic.c index 1eddae9..4deb8e1 100644 --- a/virt/kvm/ioapic.c +++ b/virt/kvm/ioapic.c @@ -180,7 +180,6 @@ int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level) if (irq >= 0 && irq < IOAPIC_NUM_PINS) { entry = ioapic->redirtbl[irq]; - level ^= entry.fields.polarity; if (!level) ioapic->irr &= ~mask;