[0/2] cpufreq: intel_pstate: Make HWP calibration work on all hybrid platforms

Message

Rafael J. Wysocki Oct. 24, 2022, 7:18 p.m. UTC

Hi All,

The HWP calibration in intel_pstate is needed to map HWP performance levels to
frequencies, which are used in the cpufreq sysfs interface, in a reliable way.
On all non-hybrid "core" platforms it is sufficient to multiply the HWP
performance levels by 100000 to obtain the corresponding frequencies, but on
hybrid ones there is a difference between P-cores and E-cores.

Previous attempts to make this work were based on using CPPC (and in particular
the nominal performance values provided by _CPC), but it turns out that the
CPPC information is not sufficiently reliable for this purpose and the only
way to do it is to use a hard-coded scaling factors for P-cores and for E-cores
(which fortunately is the same as in the non-hybrid case).  Fortunately, the
same scaling factor for P-cores works on all of the hybrid platforms to date.

The first patch in the series ensures that all of the CPUs will use correct
information from MSRs by avoiding the situations in which an MSR values read
on one CPU will be used for performance scaling of another CPU.

The second one implements the approach outlined above.

Please see the changelogs for details.

Thanks!

Comments

srinivas pandruvada Oct. 24, 2022, 10:14 p.m. UTC | #1

On Mon, 2022-10-24 at 21:18 +0200, Rafael J. Wysocki wrote:
> Hi All,
> 
> The HWP calibration in intel_pstate is needed to map HWP performance
> levels to
> frequencies, which are used in the cpufreq sysfs interface, in a
> reliable way.
> On all non-hybrid "core" platforms it is sufficient to multiply the
> HWP
> performance levels by 100000 to obtain the corresponding frequencies,
> but on
> hybrid ones there is a difference between P-cores and E-cores.
> 
> Previous attempts to make this work were based on using CPPC (and in
> particular
> the nominal performance values provided by _CPC), but it turns out
> that the
> CPPC information is not sufficiently reliable for this purpose and
> the only
> way to do it is to use a hard-coded scaling factors for P-cores and
> for E-cores
> (which fortunately is the same as in the non-hybrid case). 
> Fortunately, the
> same scaling factor for P-cores works on all of the hybrid platforms
> to date.
> 
> The first patch in the series ensures that all of the CPUs will use
> correct
> information from MSRs by avoiding the situations in which an MSR
> values read
> on one CPU will be used for performance scaling of another CPU.
> 
> The second one implements the approach outlined above.
> 
> Please see the changelogs for details.

Acked-by: Srinivas Pandruvada <[e-mail]>
Tested-by: Srinivas Pandruvada <[e-mail]>


> 
> Thanks!
> 
> 
>

Rafael J. Wysocki Oct. 25, 2022, 1:03 p.m. UTC | #2

On Tue, Oct 25, 2022 at 1:58 AM srinivas pandruvada
<[e-mail]> wrote:
>
> On Mon, 2022-10-24 at 21:18 +0200, Rafael J. Wysocki wrote:
> > Hi All,
> >
> > The HWP calibration in intel_pstate is needed to map HWP performance
> > levels to
> > frequencies, which are used in the cpufreq sysfs interface, in a
> > reliable way.
> > On all non-hybrid "core" platforms it is sufficient to multiply the
> > HWP
> > performance levels by 100000 to obtain the corresponding frequencies,
> > but on
> > hybrid ones there is a difference between P-cores and E-cores.
> >
> > Previous attempts to make this work were based on using CPPC (and in
> > particular
> > the nominal performance values provided by _CPC), but it turns out
> > that the
> > CPPC information is not sufficiently reliable for this purpose and
> > the only
> > way to do it is to use a hard-coded scaling factors for P-cores and
> > for E-cores
> > (which fortunately is the same as in the non-hybrid case).
> > Fortunately, the
> > same scaling factor for P-cores works on all of the hybrid platforms
> > to date.
> >
> > The first patch in the series ensures that all of the CPUs will use
> > correct
> > information from MSRs by avoiding the situations in which an MSR
> > values read
> > on one CPU will be used for performance scaling of another CPU.
> >
> > The second one implements the approach outlined above.
> >
> > Please see the changelogs for details.
>
> Acked-by: Srinivas Pandruvada <[e-mail]>
> Tested-by: Srinivas Pandruvada <[e-mail]>

Thank you!

As discussed offline, I'm going to fast-track this series as urgent
fixes to cover systems in the field that are likely to have problems
related to it.