From patchwork Thu Jun 13 08:54:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Xu, Haibo1" X-Patchwork-Id: 13696358 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B733E13E8A7; Thu, 13 Jun 2024 08:36:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718267793; cv=none; b=eGFj1M3Bx+jLSumlJYICIr2zozLiRvOtBp4B3zTWFGupSPMUyuXJrd3miQ/Zg+06ziwAk+NULFG3uEeF6ceABOxABtbUyr9gFP2XlEkRAPd9WXigLiQHKNEvH2ZtHZ+usb1dvD+U3IT3Ufm/o+ixcjKlOdb1YOZ2Gmfp0YzdZJ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718267793; c=relaxed/simple; bh=3ovCB/zXsuebWe0Yz4yc+d18kQMuEVZClgl8PA7HD5o=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=m9iAM+OMqQ/D5twr0Qzaj+MZkIs1d03c1Zo8XZpcvhg/qTZuigYQjHqJki5SBP6nwHFbBN+GgrSKfpToXyCzEI+4Zlg0BLXPXiELv/0ZWNRlPXc/jwL31YxBHOqviANpTVu+Cq5qrvDy7VOqk2bmiN6FddkFlHPnd7m9EHA2UE8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=FhCFEV+9; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="FhCFEV+9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1718267792; x=1749803792; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=3ovCB/zXsuebWe0Yz4yc+d18kQMuEVZClgl8PA7HD5o=; b=FhCFEV+9C2vyZt+iZPkMZKiob11F3RAFl7pHIZajmilVXbH+oYFUN8PH f6gAYlvGllyWUqaWZQXG7bytEkLF4k15UhnAGfE0TJ2fx1ykiXGxgg9nP ltR4PNvd2y4kKR6PHepzS4wpdIufmlokOQmap+Sa9Bl+6GvrBnjIS4XSt 8guTawXdY1rsAfEX3L5mRhdOL0dJYe3HY0NDYb5C9DAkLBKVmeQ9sodAS 0h7KoFdfnEuWyUnwKfJA2g1j6iOyVl6eC70pglV6qdZZcm+8BPPIwxI0q PWqCo12/5+OAlpFxGj5dENR7/Kv/Y9uZxPIXrCg9vYOvyFAlZvfZtjMdB Q==; X-CSE-ConnectionGUID: 6j9hhkotQrOTIQAuUVMeZA== X-CSE-MsgGUID: zCTwThPeSBu3TeCGlNOmkA== X-IronPort-AV: E=McAfee;i="6700,10204,11101"; a="15037733" X-IronPort-AV: E=Sophos;i="6.08,234,1712646000"; d="scan'208";a="15037733" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jun 2024 01:36:31 -0700 X-CSE-ConnectionGUID: Qv+liwW3RqmG1+jP0AhpCA== X-CSE-MsgGUID: nvdTq6xyRMCMcg4RPM/Zeg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.08,234,1712646000"; d="scan'208";a="40033609" Received: from unknown (HELO haibo-OptiPlex-7090.sh.intel.com) ([10.239.159.132]) by fmviesa008.fm.intel.com with ESMTP; 13 Jun 2024 01:36:21 -0700 From: Haibo Xu To: sunilvl@ventanamicro.com, arnd@arndb.de Cc: xiaobo55x@gmail.com, ajones@ventanamicro.com, Haibo Xu , Catalin Marinas , Will Deacon , Huacai Chen , WANG Xuerui , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J. Wysocki" , Len Brown , Greg Kroah-Hartman , Conor Dooley , Andrew Morton , Charlie Jenkins , Baoquan He , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Zong Li , Sami Tolvanen , Alexandre Ghiti , Samuel Holland , Chen Jiahao , "Russell King (Oracle)" , Jisheng Zhang , James Morse , Andy Chiu , Marc Zyngier , Thomas Gleixner , Tony Luck , Ard Biesheuvel , Dan Williams , Alison Schofield , Jonathan Cameron , Robert Richter , Yuntao Wang , Dave Jiang , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org Subject: [PATCH v4 0/4] Add ACPI NUMA support for RISC-V Date: Thu, 13 Jun 2024 16:54:32 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This patch series enable RISC-V ACPI NUMA support which was based on the recently approved ACPI ECR[1]. Patch 1/4 add RISC-V specific acpi_numa.c file to parse NUMA information from SRAT and SLIT ACPI tables. Patch 2/4 add the common SRAT RINTC affinity structure handler. Patch 3/4 change the ACPI_NUMA to a hidden option since it would be selected by default on all supported platform. Patch 4/4 replace pr_info with pr_debug in arch_acpi_numa_init() to avoid potential boot noise on ACPI platforms that are not NUMA. Based-on: https://github.com/linux-riscv/linux-riscv/tree/for-next [1] https://drive.google.com/file/d/1YTdDx2IPm5IeZjAW932EYU-tUtgS08tX/view?usp=sharing Testing: Since the ACPI AIA/PLIC support patch set is still under upstream review, hence it is tested using the poll based HVC SBI console and RAM disk. 1) Build latest Qemu with the following patch backported https://github.com/vlsunil/qemu/commit/42bd4eeefd5d4410a68f02d54fee406d8a1269b0 2) Build latest EDK-II https://github.com/tianocore/edk2/blob/master/OvmfPkg/RiscVVirt/README.md 3) Build Linux with the following configs enabled CONFIG_RISCV_SBI_V01=y CONFIG_SERIAL_EARLYCON_RISCV_SBI=y CONFIG_NONPORTABLE=y CONFIG_HVC_RISCV_SBI=y CONFIG_NUMA=y CONFIG_ACPI_NUMA=y 4) Build buildroot rootfs.cpio 5) Launch the Qemu machine qemu-system-riscv64 -nographic \ -machine virt,pflash0=pflash0,pflash1=pflash1 -smp 4 -m 8G \ -blockdev node-name=pflash0,driver=file,read-only=on,filename=RISCV_VIRT_CODE.fd \ -blockdev node-name=pflash1,driver=file,filename=RISCV_VIRT_VARS.fd \ -object memory-backend-ram,size=4G,id=m0 \ -object memory-backend-ram,size=4G,id=m1 \ -numa node,memdev=m0,cpus=0-1,nodeid=0 \ -numa node,memdev=m1,cpus=2-3,nodeid=1 \ -numa dist,src=0,dst=1,val=30 \ -kernel linux/arch/riscv/boot/Image \ -initrd buildroot/output/images/rootfs.cpio \ -append "root=/dev/ram ro console=hvc0 earlycon=sbi" [ 0.000000] ACPI: SRAT: Node 0 PXM 0 [mem 0x80000000-0x17fffffff] [ 0.000000] ACPI: SRAT: Node 1 PXM 1 [mem 0x180000000-0x27fffffff] [ 0.000000] NUMA: NODE_DATA [mem 0x17fe3bc40-0x17fe3cfff] [ 0.000000] NUMA: NODE_DATA [mem 0x27fff4c40-0x27fff5fff] ... [ 0.000000] ACPI: NUMA: SRAT: PXM 0 -> HARTID 0x0 -> Node 0 [ 0.000000] ACPI: NUMA: SRAT: PXM 0 -> HARTID 0x1 -> Node 0 [ 0.000000] ACPI: NUMA: SRAT: PXM 1 -> HARTID 0x2 -> Node 1 [ 0.000000] ACPI: NUMA: SRAT: PXM 1 -> HARTID 0x3 -> Node 1 Reviewed-by: Hanjun Guo --- Changes since v3 - Rebase to linux-riscv/for-next(Linux 6.10-rc1) - Remove original patch 1/6 since it had been merged through ACPICA pull(commit fe1c408d50604f) - Remove original patch 4/6 since the related changes was introduced in commit 3a785e19f43267 Haibo Xu (4): ACPI: RISCV: Add NUMA support based on SRAT and SLIT ACPI: NUMA: Add handler for SRAT RINTC affinity structure ACPI: NUMA: change the ACPI_NUMA to a hidden option ACPI: NUMA: replace pr_info with pr_debug in arch_acpi_numa_init arch/arm64/Kconfig | 1 - arch/loongarch/Kconfig | 1 - arch/riscv/include/asm/acpi.h | 15 +++- arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/acpi.c | 5 -- arch/riscv/kernel/acpi_numa.c | 131 ++++++++++++++++++++++++++++++++++ arch/riscv/kernel/setup.c | 4 +- arch/riscv/kernel/smpboot.c | 2 - drivers/acpi/numa/Kconfig | 5 +- drivers/acpi/numa/srat.c | 32 ++++++++- drivers/base/arch_numa.c | 2 +- include/linux/acpi.h | 6 ++ 12 files changed, 187 insertions(+), 18 deletions(-) create mode 100644 arch/riscv/kernel/acpi_numa.c