From patchwork Tue Dec 3 16:41:29 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjun Guo X-Patchwork-Id: 3277761 Return-Path: X-Original-To: patchwork-linux-acpi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2263F9F380 for ; Tue, 3 Dec 2013 16:43:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EE26A2015E for ; Tue, 3 Dec 2013 16:43:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BAF1020173 for ; Tue, 3 Dec 2013 16:43:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754082Ab3LCQly (ORCPT ); Tue, 3 Dec 2013 11:41:54 -0500 Received: from mail-pb0-f42.google.com ([209.85.160.42]:36416 "EHLO mail-pb0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754200Ab3LCQlv (ORCPT ); Tue, 3 Dec 2013 11:41:51 -0500 Received: by mail-pb0-f42.google.com with SMTP id uo5so21481815pbc.29 for ; Tue, 03 Dec 2013 08:41:50 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=lvuvPoYnqKcaQL9Mv3P61N+m7Zyf/JigU8htz4yPujo=; b=G/b3+2vO5iCTsyhfeRfk6CutS2RM5eSvFYYZ/gNfu3nd5gl4BPN57UV/Uydp+WFZXt JyFVpCNXqdjzkpLVO6FIVKXjZcDcJLTLPipOMn1Y618XbXKzrcCKkiQXfTiaYdCIB1Ds 1CEkM9Va7Lk61/f047G1FIM8a7OCw6chMGsWpJWJ7w2mTWbzb01YUy04vQzMlTAyuyN9 RtadIbWfyUfiWZLfG6fkY0gZ/DTsUXtjWOHJQZh+qGLqHUOJ1UCasBcgOMZaH9ubGaAt MKf+3dQiscWXg38HzeyJ675fw1XgX+8qIPoCLt4ua/bHj0WUpg4r9hSc2N3jKAw1wK5o t2mw== X-Gm-Message-State: ALoCoQn/Q9tpUsfc254Xx6IE/CY7lBDoP3Vh5XZlpXspvPhiSkqcP9qZnALRK2FGqbTpJqY0PLjb X-Received: by 10.66.118.71 with SMTP id kk7mr76477533pab.14.1386088910553; Tue, 03 Dec 2013 08:41:50 -0800 (PST) Received: from localhost ([61.148.199.138]) by mx.google.com with ESMTPSA id om6sm41401605pbc.43.2013.12.03.08.41.37 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 03 Dec 2013 08:41:49 -0800 (PST) From: Hanjun Guo To: "Rafael J. Wysocki" , Catalin Marinas , Will Deacon , Russell King - ARM Linux , Daniel Lezcano Cc: linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Grant Likely , Matthew Garrett , Olof Johansson , Linus Walleij , Bjorn Helgaas , Rob Herring , Mark Rutland , Jon Masters , patches@linaro.org, linux-kernel@vger.kernel.org, linaro-kernel@lists.linaro.org, linaro-acpi@lists.linaro.org, Hanjun Guo Subject: [RFC part3 PATCH 0/2] Using ACPI GTDT table to initialize arch timer Date: Wed, 4 Dec 2013 00:41:29 +0800 Message-Id: <1386088891-2917-1-git-send-email-hanjun.guo@linaro.org> X-Mailer: git-send-email 1.7.9.5 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This is the last part of patch set for core of ARM64 ACPI, and is based on the patch set part2 "Using ACPI MADT table to initialise SMP and GIC". ACPI GTDT (Generic Timer Description Table) is used for ARM/ARM64 only, and contains the information for arch timer initialisation. This patch trys to convert the arch timer to ACPI using GTDT. After this patch set was posted, we already finished the SMP, GIC and arch timer initialisation, which all are essential for ARM64 core system running, then we will focus on converting the device drivers to ACPI. Here is the GTDT ASL code I used: --- platforms/foundation-v8.acpi/gtdt.asl | 35 ++++++++++++++++++++++----------- 1 file changed, 23 insertions(+), 12 deletions(-) Hanjun Guo (2): clocksource / arch_timer: Use ACPI GTDT table to initialize arch timer ARM64 / clocksource: Use arch_timer_acpi_init() arch/arm64/kernel/time.c | 4 ++ drivers/clocksource/arm_arch_timer.c | 129 ++++++++++++++++++++++++++++++---- include/clocksource/arm_arch_timer.h | 7 +- 3 files changed, 124 insertions(+), 16 deletions(-) diff --git a/platforms/foundation-v8.acpi/gtdt.asl b/platforms/foundation-v8.acpi/gtdt.asl index 18c821a..714d61c 100644 --- a/platforms/foundation-v8.acpi/gtdt.asl +++ b/platforms/foundation-v8.acpi/gtdt.asl @@ -1,5 +1,6 @@ /* * Copyright (c) 2013, Al Stone + * Hanjun Guo * * [GTDT] Generic Timer Description Table * Format: [ByteLength] FieldName : HexFieldValue @@ -21,22 +22,32 @@ [0004] Flags (decoded below) : 00000001 Memory Present : 1 -[0004] Secure PL1 Interrupt : 00000000 -[0004] SPL1 Flags (decoded below) : 00000000 - Trigger Mode : 0 +/* In Foundation model's dts file, the last cell of interrupts + * is 0xff01, it means its cpu mask is FF, and trigger type + * and flag is 1 = low-to-high edge triggered. + * + * so in ACPI the Trigger Mode is 1 - Edge triggered, and + * Polarity is 0 - Active high as ACPI spec describled. + * + * using direct mapping for hwirqs, it means that we using + * ID [16, 31] for PPI, not [0, 15] used in FDT. + */ +[0004] Secure PL1 Interrupt : 0000001d +[0004] SPL1 Flags (decoded below) : 00000001 + Trigger Mode : 1 Polarity : 0 -[0004] Non-Secure PL1 Interrupt : 00000000 -[0004] NSPL1 Flags (decoded below) : 00000000 - Trigger Mode : 0 +[0004] Non-Secure PL1 Interrupt : 0000001e +[0004] NSPL1 Flags (decoded below) : 00000001 + Trigger Mode : 1 Polarity : 0 -[0004] Virtual Timer Interrupt : 00000000 -[0004] VT Flags (decoded below) : 00000000 - Trigger Mode : 0 +[0004] Virtual Timer Interrupt : 0000001b +[0004] VT Flags (decoded below) : 00000001 + Trigger Mode : 1 Polarity : 0 -[0004] Non-Secure PL2 Interrupt : 00000000 -[0004] NSPL2 Flags (decoded below) : 00000000 - Trigger Mode : 0 +[0004] Non-Secure PL2 Interrupt : 0000001a +[0004] NSPL2 Flags (decoded below) : 00000001 + Trigger Mode : 1 Polarity : 0