From patchwork Fri Jan 17 12:25:11 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjun Guo X-Patchwork-Id: 3504231 Return-Path: X-Original-To: patchwork-linux-acpi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E6654C02DC for ; Fri, 17 Jan 2014 12:55:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 13BE22015E for ; Fri, 17 Jan 2014 12:55:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4D7422012F for ; Fri, 17 Jan 2014 12:55:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751484AbaAQMzv (ORCPT ); Fri, 17 Jan 2014 07:55:51 -0500 Received: from mail-pd0-f181.google.com ([209.85.192.181]:33435 "EHLO mail-pd0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751326AbaAQMzu (ORCPT ); Fri, 17 Jan 2014 07:55:50 -0500 Received: by mail-pd0-f181.google.com with SMTP id y10so417932pdj.26 for ; Fri, 17 Jan 2014 04:55:49 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hlpZUQE/aVVDpGgkUJ6uz0q3hhYK6mPjskIw/Hgwlf0=; b=h6yfKQ898fL47xU/N7hg0JYXroI6Aw2to6tv2Jz8qpDneLBEgSmz4z4MiveHyG3S1x +c6qgQZCU/tBdUOoqZbYvE9cR981X2Vz4QVloxmXMWzL82fZ6KZrygnpSvEkwkhu2dT/ RUV5aOA9YrmXTInlWGTDEnRP0+K6qYusoeaJIP5xziElpo21r4rrgcy5+lyldrXaEghx QJqH3fPT3Vjpto2RTdjCR0GX4inyxZozCirJW2xttCMJBDsuQa8SWjfZGUZ8muQW+pCg hPYDebqlGFwDbqe+8lt8iXUSf00jgLRSI2SUWgDVWU4ABnSFMniwKyh1c1jPTZqjSRnX DW6A== X-Gm-Message-State: ALoCoQmk2cG/1/qMhEjqkXki/B446Fmhj4dS0dqp5aqqpI+iZr1+QDyZjq2hEqdjPTnLLUikUbXk X-Received: by 10.68.134.98 with SMTP id pj2mr1953676pbb.110.1389963349848; Fri, 17 Jan 2014 04:55:49 -0800 (PST) Received: from localhost ([218.17.215.175]) by mx.google.com with ESMTPSA id jn12sm22627608pbd.37.2014.01.17.04.54.19 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 17 Jan 2014 04:55:49 -0800 (PST) From: Hanjun Guo To: "Rafael J. Wysocki" , Catalin Marinas , Will Deacon , Russell King - ARM Linux Cc: linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Grant Likely , Matthew Garrett , Olof Johansson , Linus Walleij , Bjorn Helgaas , Rob Herring , Mark Rutland , Arnd Bergmann , patches@linaro.org, linux-kernel@vger.kernel.org, linaro-kernel@lists.linaro.org, linaro-acpi@lists.linaro.org, Charles.Garcia-Tobin@arm.com, Hanjun Guo , Amit Daniel Kachhap Subject: [PATCH 17/20] clocksource / arch_timer: Use ACPI GTDT table to initialize arch timer Date: Fri, 17 Jan 2014 20:25:11 +0800 Message-Id: <1389961514-13562-18-git-send-email-hanjun.guo@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1389961514-13562-1-git-send-email-hanjun.guo@linaro.org> References: <1389961514-13562-1-git-send-email-hanjun.guo@linaro.org> Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Spam-Status: No, score=-6.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_WEB, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP ACPI GTDT (Generic Timer Description Table) contains information for arch timer initialization, this patch use this table to probe arm timer. GTDT table is used for ARM/ARM64 only, please refer to chapter 5.2.24 of ACPI 5.0 spec for detailed inforamtion Signed-off-by: Amit Daniel Kachhap Signed-off-by: Hanjun Guo --- drivers/clocksource/arm_arch_timer.c | 100 +++++++++++++++++++++++++++++----- 1 file changed, 85 insertions(+), 15 deletions(-) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 95fb944..1fa5f67 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -632,20 +633,8 @@ static void __init arch_timer_common_init(void) arch_timer_arch_init(); } -static void __init arch_timer_init(struct device_node *np) +static void __init arch_timer_init(void) { - int i; - - if (arch_timers_present & ARCH_CP15_TIMER) { - pr_warn("arch_timer: multiple nodes in dt, skipping\n"); - return; - } - - arch_timers_present |= ARCH_CP15_TIMER; - for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++) - arch_timer_ppi[i] = irq_of_parse_and_map(np, i); - arch_timer_detect_rate(NULL, np); - /* * If HYP mode is available, we know that the physical timer * has been configured to be accessible from PL1. Use it, so @@ -667,8 +656,89 @@ static void __init arch_timer_init(struct device_node *np) arch_timer_register(); arch_timer_common_init(); } -CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_init); -CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_init); + +static void __init arch_timer_of_init(struct device_node *np) +{ + int i; + + if (arch_timers_present & ARCH_CP15_TIMER) { + pr_warn("arch_timer: multiple nodes in dt, skipping\n"); + return; + } + + arch_timers_present |= ARCH_CP15_TIMER; + for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++) + arch_timer_ppi[i] = irq_of_parse_and_map(np, i); + arch_timer_detect_rate(NULL, np); + + arch_timer_init(); +} +CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init); +CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init); + +#ifdef CONFIG_ACPI +static void __init register_arch_interrupt(u32 interrupt, u32 flags, + int *arch_timer_ppi) +{ + int trigger, polarity; + + if (!interrupt || !arch_timer_ppi) + return; + + trigger = (flags & ACPI_GTDT_INTERRUPT_MODE) ? ACPI_EDGE_SENSITIVE + : ACPI_LEVEL_SENSITIVE; + + polarity = (flags & ACPI_GTDT_INTERRUPT_POLARITY) ? ACPI_ACTIVE_LOW + : ACPI_ACTIVE_HIGH; + + *arch_timer_ppi = acpi_register_gsi(NULL, interrupt, trigger, + polarity); +} + +static int __init acpi_parse_gtdt(struct acpi_table_header *table) +{ + struct acpi_table_gtdt *gtdt; + + gtdt = (struct acpi_table_gtdt *)table; + if (!gtdt) + return -EINVAL; + + arch_timer_rate = arch_timer_get_cntfrq(); + + if (!arch_timer_rate) { + pr_warn("arch_timer: Could not get frequency from CNTFREG\n"); + return -EINVAL; + } + + register_arch_interrupt(gtdt->secure_pl1_interrupt, + gtdt->secure_pl1_flags, &arch_timer_ppi[PHYS_SECURE_PPI]); + + register_arch_interrupt(gtdt->non_secure_pl1_interrupt, + gtdt->non_secure_pl1_flags, &arch_timer_ppi[PHYS_NONSECURE_PPI]); + + register_arch_interrupt(gtdt->virtual_timer_interrupt, + gtdt->virtual_timer_flags, &arch_timer_ppi[VIRT_PPI]); + + register_arch_interrupt(gtdt->non_secure_pl2_interrupt, + gtdt->non_secure_pl2_flags, &arch_timer_ppi[HYP_PPI]); + + return 0; +} + +void __init arch_timer_acpi_init(struct acpi_table_header *table) +{ + if (arch_timers_present & ARCH_CP15_TIMER) { + pr_warn("arch_timer: already initialized, skipping\n"); + return; + } + + if (acpi_parse_gtdt(table)) + return; + + arch_timers_present |= ARCH_CP15_TIMER; + arch_timer_init(); +} +#endif static void __init arch_timer_mem_init(struct device_node *np) {