From patchwork Fri Feb 27 15:00:36 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Nowicki X-Patchwork-Id: 5901091 Return-Path: X-Original-To: patchwork-linux-acpi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 0E6F59F37F for ; Fri, 27 Feb 2015 15:03:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5376220263 for ; Fri, 27 Feb 2015 15:03:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 74ABD20148 for ; Fri, 27 Feb 2015 15:03:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755220AbbB0PDm (ORCPT ); Fri, 27 Feb 2015 10:03:42 -0500 Received: from mail-la0-f47.google.com ([209.85.215.47]:36036 "EHLO mail-la0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752983AbbB0PAG (ORCPT ); Fri, 27 Feb 2015 10:00:06 -0500 Received: by labgq15 with SMTP id gq15so18166880lab.3 for ; Fri, 27 Feb 2015 07:00:04 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zuXkt7WwSYbrIw8I01n9FZZuSVlKsomiQ1Qg+TxqeQ0=; b=EvMbcgoMmnn5KngAS3vgYIiwl08DrVLe74umzvVM/UFG8kkxnSQ6QDQLhHewwvzrlq BU0olXPkgBLU7cHdGoudeSsNNIuPKiK5hBYy7QUH/K/zlRnrZkoPpV5dats1RJT1T3C+ k6UP5/8al6fdDHj1vlzMTvBvvOdUWPtgt5jbLErxX8I3ORxs3W37u0xL7pYABeL//WGv 8Wv9rZiRkLlCzVzQYgtV2Eq8MnkbofOl5yS6K4O2zU04mQkTnpCcK8IXgOmfbtTgHLIz 15I/Xa/1Z2TIRtjBPDBrXtOF53og/jBs3tJXOvLPq3oYO+hsK1D7zTXPPnZWqGYz3icA CKfg== X-Gm-Message-State: ALoCoQl3p0QPl02sYYCy/X8YTfnoIwET+BcDN6ffyyH0EqrDYXQX7C14qdsAwrjuSc6rk646TNXe X-Received: by 10.152.43.101 with SMTP id v5mr12853526lal.83.1425049204858; Fri, 27 Feb 2015 07:00:04 -0800 (PST) Received: from tn-HP-4.semihalf.com ([80.82.22.190]) by mx.google.com with ESMTPSA id p7sm886055lap.18.2015.02.27.07.00.03 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 27 Feb 2015 07:00:04 -0800 (PST) From: Tomasz Nowicki To: bhelgaas@google.com, wangyijing@huawei.com, arnd@arndb.de, hanjun.guo@linaro.org, Liviu.Dudau@arm.com, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, rjw@rjwysocki.net, al.stone@linaro.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, x86@kernel.org, linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org, linaro-acpi@lists.linaro.org, Tomasz Nowicki Subject: [PATCH v2 1/9] x86, pci: Clean up comment about buggy MMIO config space access for AMD Fam10h CPUs. Date: Fri, 27 Feb 2015 16:00:36 +0100 Message-Id: <1425049244-19331-2-git-send-email-tomasz.nowicki@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1425049244-19331-1-git-send-email-tomasz.nowicki@linaro.org> References: <1425049244-19331-1-git-send-email-tomasz.nowicki@linaro.org> Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP - fix typo - improve explanation - add reference to the related document Signed-off-by: Tomasz Nowicki --- arch/x86/include/asm/pci_x86.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h index 164e3f8..eddf8f0 100644 --- a/arch/x86/include/asm/pci_x86.h +++ b/arch/x86/include/asm/pci_x86.h @@ -154,10 +154,13 @@ extern struct list_head pci_mmcfg_list; /* * AMD Fam10h CPUs are buggy, and cannot access MMIO config space - * on their northbrige except through the * %eax register. As such, you MUST - * NOT use normal IOMEM accesses, you need to only use the magic mmio-config + * on their northbridge except through the * %eax register. As such, you MUST + * NOT use normal IOMEM accesses, you need to only use the magic mmio_config_* * accessor functions. - * In fact just use pci_config_*, nothing else please. + * + * Please refer to the following doc: + * "BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors", + * rev. 3.48, sec 2.11.1, "MMIO Configuration Coding Requirements". */ static inline unsigned char mmio_config_readb(void __iomem *pos) {