From patchwork Fri Apr 17 07:14:50 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Nowicki X-Patchwork-Id: 6228751 Return-Path: X-Original-To: patchwork-linux-acpi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 799ED9F2EC for ; Fri, 17 Apr 2015 07:18:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B625320320 for ; Fri, 17 Apr 2015 07:18:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7F7A820351 for ; Fri, 17 Apr 2015 07:18:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932120AbbDQHSb (ORCPT ); Fri, 17 Apr 2015 03:18:31 -0400 Received: from mail-lb0-f171.google.com ([209.85.217.171]:33065 "EHLO mail-lb0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752426AbbDQHPk (ORCPT ); Fri, 17 Apr 2015 03:15:40 -0400 Received: by lbbzk7 with SMTP id zk7so76060178lbb.0 for ; Fri, 17 Apr 2015 00:15:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XubwWYOsv3Nxc7e+lrSYN1gukLOM4gdx/jBhbo4T9uw=; b=ADsTzTflF6m3zldwTbKf7ueTmDobLIqiemrkZFz0EdFNAtZ1ssRrZztj5bHvLHpkrr FD0kl4X+T3wOgjpLS7vjwVotsq5L9jx3+COcQ/A39NZxwr39zotSmspEFYYgO/q8b5Ap WjA+kDkbDC3xfFOBItAaOpFg5+DJAjDtSd1EuaS+fx8GSzECPQBcNBuj3XcTVyIXikFt Xn6ji9e1C/j4dw3KCvfKWITylktJF5bd1tvT9Lhl75UyLkeo5DM6tEoyt1hdcl6MFWqH ki059y+LIiK5BrfeqWoOppJm9CreR2NBMVQJ7lfxyhXkAFI2PQg/Mv2eZvFJ77BsShKd xYMg== X-Gm-Message-State: ALoCoQnRmw4VCriewGqUjJE9UhS7S41yMx0EIfj4KmKk/qitm+Ly/8wDJmTr34X/Q9CmE+cXQ4JC X-Received: by 10.112.147.201 with SMTP id tm9mr1374641lbb.40.1429254938978; Fri, 17 Apr 2015 00:15:38 -0700 (PDT) Received: from tn-HP-4.semihalf.local ([80.82.22.190]) by mx.google.com with ESMTPSA id yq18sm2215742lbb.47.2015.04.17.00.15.37 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 17 Apr 2015 00:15:38 -0700 (PDT) From: Tomasz Nowicki To: bhelgaas@google.com, wangyijing@huawei.com, arnd@arndb.de, hanjun.guo@linaro.org, Liviu.Dudau@arm.com, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, rjw@rjwysocki.net, al.stone@linaro.org, lorenzo.pieralisi@arm.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, x86@kernel.org, linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org, linaro-acpi@lists.linaro.org, Tomasz Nowicki Subject: [PATCH v5 1/9] x86, pci: Clean up comment about buggy MMIO config space access for AMD Fam10h CPUs. Date: Fri, 17 Apr 2015 09:14:50 +0200 Message-Id: <1429254898-32743-2-git-send-email-tomasz.nowicki@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1429254898-32743-1-git-send-email-tomasz.nowicki@linaro.org> References: <1429254898-32743-1-git-send-email-tomasz.nowicki@linaro.org> Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP - fix typo - improve explanation - add reference to the related document Signed-off-by: Tomasz Nowicki --- arch/x86/include/asm/pci_x86.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h index fa1195d..d024f4d 100644 --- a/arch/x86/include/asm/pci_x86.h +++ b/arch/x86/include/asm/pci_x86.h @@ -152,10 +152,13 @@ extern struct list_head pci_mmcfg_list; /* * AMD Fam10h CPUs are buggy, and cannot access MMIO config space - * on their northbrige except through the * %eax register. As such, you MUST - * NOT use normal IOMEM accesses, you need to only use the magic mmio-config + * on their northbridge except through the * %eax register. As such, you MUST + * NOT use normal IOMEM accesses, you need to only use the magic mmio_config_* * accessor functions. - * In fact just use pci_config_*, nothing else please. + * + * Please refer to the following doc: + * "BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors", + * rev. 3.48, sec 2.11.1, "MMIO Configuration Coding Requirements". */ static inline unsigned char mmio_config_readb(void __iomem *pos) {