| Message ID | 20130318191903.GS9021@phenom.ffwll.local (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
On Mon, Mar 18, 2013 at 08:19:03PM +0100, Daniel Vetter wrote: > On Mon, Mar 18, 2013 at 10:12:49AM +0100, Jiri Kosina wrote: > > On Fri, 15 Mar 2013, Yinghai Lu wrote: > > > > > > Just a datapoint -- I have put a trivial debugging patch in place, and it > > > > reveals that "nobody cared" for irq 16 happens long after last > > > > > > > > I915_WRITE(GMBUS4 + reg_offset, 0); > > > > > > > > has been performed in gmbus_wait_hw_status(). On the other hand, if I > > > > comment out both GMBUS4 register offset writes in gmbus_wait_hw_status(), > > > > then it of course falls back to GPIO bit-banging, but the "nobody cared" > > > > for irq 16 is gone. > > > > > > > > So it seems like something gets severely confused by the I915_WRITE to > > > > GMBUS4 + reg_offset. So far this seems to have been reported solely on > > > > Lenovos as far as I can see (although a completely different types), so it > > > > might be some platform-specific quirk? > > > > > > > > Honestly, I still don't understand how all the GMBUS stuff relates to IRQ > > > > 16 at all. > > > > > > that device is using > > > i915 0000:00:02.0: irq 44 for MSI/MSI-X > > > > > > so can you try to boot with pci=nomsi? > > > > Yes, switching from MSI to IO-APIC-fasteoi makes the report about lost > > interrupts go away. > > > > My understanding from the other mail is that DAniel Vetter already has an > > idea what might be going wrong with IRQ acking on GM45 chipsets; hopefully > > this datapoint regarding MSI will fit into it. > > Yep, there's a big comment in the irq handler for that chipset that we > have a gaping race with when using MSI interrupts. Although the comment > bodly claims that the race is small enough to avoid the dreaded "nobody > cared" message. Looks like gmbus is good at hitting that race - on newer > chips it already brought up a similar race in handling pch interrupts. > > Can you please give the below patch a whirl? It removes the probably race > msi race avoidance code and replaces it with the same trick Paulo used to > fix pch irq handling races. Still nobody cares about irq16. -Chris
On Mon, 18 Mar 2013, Daniel Vetter wrote: > Yep, there's a big comment in the irq handler for that chipset that we > have a gaping race with when using MSI interrupts. Although the comment > bodly claims that the race is small enough to avoid the dreaded "nobody > cared" message. Looks like gmbus is good at hitting that race - on newer > chips it already brought up a similar race in handling pch interrupts. I see ... will target my focus in that direction, thanks. > Can you please give the below patch a whirl? It removes the probably race > msi race avoidance code and replaces it with the same trick Paulo used to > fix pch irq handling races. Unfortunately it didn't change anything, the spurious interrupt report is still there.
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 3c7bb04..13de12e 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2684,7 +2684,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) { struct drm_device *dev = (struct drm_device *) arg; drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; - u32 iir, new_iir; + u32 iir, new_iir, ier; u32 pipe_stats[I915_MAX_PIPES]; unsigned long irqflags; int irq_received; @@ -2692,9 +2692,14 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) atomic_inc(&dev_priv->irq_received); + /* irq race avoidance, copy&pasta from Paulo's PCH irq fix */ + ier = I915_READ(IER); + I915_WRITE(IER, 0); + POSTING_READ(IER); + iir = I915_READ(IIR); - for (;;) { + do { bool blc_event = false; irq_received = iir != 0; @@ -2792,7 +2797,10 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) * stray interrupts. */ iir = new_iir; - } + } while (0); + + I915_WRITE(IER, ier); + POSTING_READ(IER); i915_update_dri1_breadcrumb(dev);