From patchwork Thu Apr 17 20:20:33 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 4010581 Return-Path: X-Original-To: patchwork-linux-acpi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 61F2E9F499 for ; Thu, 17 Apr 2014 20:20:43 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7BE30202D1 for ; Thu, 17 Apr 2014 20:20:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 77FF5202FE for ; Thu, 17 Apr 2014 20:20:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751129AbaDQUUj (ORCPT ); Thu, 17 Apr 2014 16:20:39 -0400 Received: from mail-pa0-f49.google.com ([209.85.220.49]:54454 "EHLO mail-pa0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750893AbaDQUUi (ORCPT ); Thu, 17 Apr 2014 16:20:38 -0400 Received: by mail-pa0-f49.google.com with SMTP id lj1so730048pab.22 for ; Thu, 17 Apr 2014 13:20:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=subject:to:from:cc:date:message-id:user-agent:mime-version :content-type:content-transfer-encoding; bh=n94HCIqb/PmbcpgRUhaqH4eOIaol07q1QelanwBeYR8=; b=b5WcbnAOXjZVqvnmiE+cUE/MfHePmHgg3uyTj9/s+vQQDArylNqGj5V0roKNf5FhkQ ctVbzFlOk+chaK1lXi9BS+404nnsMN0p3a5rCYMXM76SatnHaexE5o8HoXcIjLfQWEp0 BUSIyEV4JjCgUANqQHPDkOQ8U7w5Q9bZ4Iqaxd8CrRgqeZuM9ynvnW8SbczOTAX12h4y BaQPvBIir6HpyaTmTCwg1VOpn7oIeWKecWSBd2pVjWKGxgu2zcO+Beqi6PyowhlkM7xu g1wKNUhqFns1ZBMzZRIAR2NFk1hQlZp44R7ZvDPtFGnff/IiBe6VpkFs77id+wtR4Y3j 262A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:subject:to:from:cc:date:message-id:user-agent :mime-version:content-type:content-transfer-encoding; bh=n94HCIqb/PmbcpgRUhaqH4eOIaol07q1QelanwBeYR8=; b=LVG/3YbT5QhjNDWlj1/F3JGLpDYLj+ij71erzBv6+PUYb8kEKY+CXyAHYEvF291BDp 0WrsUgWMtGX55qLid75UsignOvgm756+MNiyaZFdan2d6siy96HDhlu+eL3aQU4ZRso9 nnv7yhSUwqratswRWbRqNv2Cdxacy7/HMfa6E1RhjhsF2U1iAB1krBMZ+Zppk2qTLWFM Va2hi0CaxmCoo6934Fw5BZ27BXEICJ1SfeWc9S0ysfEXwURpv8NcFHeCd6Gx6ZI0mpOA z/gCJyI0a+iHKiqs26CfO/F+ETmod7+IdPCaBW15ggLmM6QAdRDJZliJk/7NcSURMm6T 4D6g== X-Gm-Message-State: ALoCoQmJonJUkWCpiU/gndgcdc0KgpxQaZ0ABmvEfmni/AlCeriy6quaWi6VL0d47HmiIgJu44d24BSLoYKTAzxUFbo6751/bKNco7Wx9zfAfiBNY6QX0DgiCLSFS2pJS2tX36UjPRapi1p68949yvWDWQAfOpfMiZG+IVajYsJquO6BPn9MvCcalPFWzGbZaOps9uo3AsSBTs7KJcQQrdvVgVxtlkeAhg== X-Received: by 10.68.230.41 with SMTP id sv9mr17987809pbc.23.1397766037646; Thu, 17 Apr 2014 13:20:37 -0700 (PDT) Received: from localhost ([172.26.50.21]) by mx.google.com with ESMTPSA id sh5sm55400651pbc.21.2014.04.17.13.20.35 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 17 Apr 2014 13:20:37 -0700 (PDT) Subject: [PATCH] PNP: Work around BIOS defects in Intel MCH area reporting To: "Rafael J. Wysocki" From: Bjorn Helgaas Cc: Aaron Lu , linux-pci@vger.kernel.org, x86@kernel.org, linux-kernel@vger.kernel.org, Stephane Eranian , linux-acpi@vger.kernel.org, Borislav Petkov , "H. Peter Anvin" , Zheng Z Yan , Dave Jones , Rui Zhang , Yinghai Lu Date: Thu, 17 Apr 2014 14:20:33 -0600 Message-ID: <20140417202033.7057.98414.stgit@bhelgaas-glaptop.roam.corp.google.com> User-Agent: StGit/0.16 MIME-Version: 1.0 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Work around BIOSes that don't report the entire Intel MCH area. MCHBAR is not an architected PCI BAR, so MCH space is usually reported as a PNP0C02 resource. The MCH space was once 16KB, but is 32KB in newer parts. Some BIOSes still report a PNP0C02 resource that is only 16KB, which means the rest of the MCH space is consumed but unreported. This can cause resource map sanity check warnings or (theoretically) a device conflict if we assigned the unreported space to another device. The Intel perf event uncore driver tripped over this when it claimed the MCH region: resource map sanity check conflict: 0xfed10000 0xfed15fff 0xfed10000 0xfed13fff pnp 00:01 Info: mapping multiple BARs. Your kernel is fine. To prevent this, if we find a PNP0C02 resource that covers part of the MCH space, extend it to cover the entire space. Link: http://lkml.kernel.org/r/20140224162400.GE16457@pd.tnic Reported-by: Borislav Petkov Tested-by: Borislav Petkov Signed-off-by: Bjorn Helgaas Acked-by: Borislav Petkov --- drivers/pnp/quirks.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pnp/quirks.c b/drivers/pnp/quirks.c index 258fef272ea7..90b8c12c220d 100644 --- a/drivers/pnp/quirks.c +++ b/drivers/pnp/quirks.c @@ -334,6 +334,79 @@ static void quirk_amd_mmconfig_area(struct pnp_dev *dev) } #endif +/* Device IDs of parts that have 32KB MCH space */ +static const unsigned int mch_quirk_devices[] = { + 0x0154, /* Ivy Bridge */ + 0x0c00, /* Haswell */ +}; + +static struct pci_dev *get_intel_host(void) +{ + int i; + struct pci_dev *host; + + for (i = 0; i < ARRAY_SIZE(mch_quirk_devices); i++) { + host = pci_get_device(PCI_VENDOR_ID_INTEL, mch_quirk_devices[i], + NULL); + if (host) + return host; + } + return NULL; +} + +static void quirk_intel_mch(struct pnp_dev *dev) +{ + struct pci_dev *host; + u32 addr_lo, addr_hi; + struct pci_bus_region region; + struct resource mch; + struct pnp_resource *pnp_res; + struct resource *res; + + host = get_intel_host(); + if (!host) + return; + + /* + * MCHBAR is not an architected PCI BAR, so MCH space is usually + * reported as a PNP0C02 resource. The MCH space was originally + * 16KB, but is 32KB in newer parts. Some BIOSes still report a + * PNP0C02 resource that is only 16KB, which means the rest of the + * MCH space is consumed but unreported. + */ + + /* + * Read MCHBAR for Host Member Mapped Register Range Base + * https://www-ssl.intel.com/content/www/us/en/processors/core/4th-gen-core-family-desktop-vol-2-datasheet + * Sec 3.1.12. + */ + pci_read_config_dword(host, 0x48, &addr_lo); + region.start = addr_lo & ~0x7fff; + pci_read_config_dword(host, 0x4c, &addr_hi); + region.start |= (dma_addr_t) addr_hi << 32; + region.end = region.start + 32*1024 - 1; + + memset(&mch, 0, sizeof(mch)); + mch.flags = IORESOURCE_MEM; + pcibios_bus_to_resource(host->bus, &mch, ®ion); + + list_for_each_entry(pnp_res, &dev->resources, list) { + res = &pnp_res->res; + if (res->end < mch.start || res->start > mch.end) + continue; /* no overlap */ + if (res->start == mch.start && res->end == mch.end) + continue; /* exact match */ + + dev_info(&dev->dev, FW_BUG "PNP resource %pR covers only part of %s Intel MCH; extending to %pR\n", + res, pci_name(host), &mch); + res->start = mch.start; + res->end = mch.end; + break; + } + + pci_dev_put(host); +} + /* * PnP Quirks * Cards or devices that need some tweaking due to incomplete resource info @@ -364,6 +437,7 @@ static struct pnp_fixup pnp_fixups[] = { #ifdef CONFIG_AMD_NB {"PNP0c01", quirk_amd_mmconfig_area}, #endif + {"PNP0c02", quirk_intel_mch}, {""} };