From patchwork Mon Apr 21 22:17:21 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 4027291 Return-Path: X-Original-To: patchwork-linux-acpi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9CD009F387 for ; Mon, 21 Apr 2014 22:17:30 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8762E20357 for ; Mon, 21 Apr 2014 22:17:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8BBBD2024C for ; Mon, 21 Apr 2014 22:17:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754667AbaDUWR1 (ORCPT ); Mon, 21 Apr 2014 18:17:27 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:52558 "EHLO mail-pb0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754599AbaDUWRZ (ORCPT ); Mon, 21 Apr 2014 18:17:25 -0400 Received: by mail-pb0-f45.google.com with SMTP id uo5so4202462pbc.32 for ; Mon, 21 Apr 2014 15:17:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=subject:to:from:cc:date:message-id:user-agent:mime-version :content-type:content-transfer-encoding; bh=MefENB7P5SaXtbbutqHOCtf0ZCivPg2p6+SHqc9etIg=; b=jUVmKZcQSLIic5fUNTmHCzL/hchXE6aBWsR555BXFBLVIzbZ5AmMFjhhaA+hBGjnB0 ToQeGG1O0zrxaHcEyuJlGagdEh5Psz1sCUu2mnCqhftNvFYs5dqq3TLZXnwVsoFM3MzL Wm3DhOYj/gJWabK2Wzt6UeoGGKUQfArcZ9WwDedBCEvBseJBnaao8W/ZTlkCZaEROdaf 9apGZelkPlDhbOEAragHMFVHjWIaeeigkPaNrplVkHL6DZI73+q5rE2dGR7Hvczyqx8d Yj8SUZTOU56JSgerI/Twnlok2KPgUyo+Mmqnt6+quJsuG3dM9IpkS/g5WZYvN9gtmZDS sCfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:subject:to:from:cc:date:message-id:user-agent :mime-version:content-type:content-transfer-encoding; bh=MefENB7P5SaXtbbutqHOCtf0ZCivPg2p6+SHqc9etIg=; b=mGzDjymoYkWCoJM0/FQh4nJm0cU+4Qz/iKpafcdKBNle7R5acYZfSYYJ/3fbTkarpl NTxP9NgTqnO+OC2b1fxIzUVeW1FHOctMRplUB7uUSdzZ9XnoQzh5mPFuDv16BewqIK5I k7FJEWCzReQnyEDOuFfsTcAkYAUzLWHNkNWcaf+cneCjsgMpgGVIkEFWYSXszpUydfxC GIULIyOnfooyxNLJpyUvu5ltJw/eFwZmC6EqF8qh20++vt5u2IjxuQtFZhE6Cd0yjMIp w6vjR/tfzkppKjRtMZimYkxBcmz4EGCu1vlzHMF5UHmzwD/t/uFXiwtUhfxho5KxF8CS D4lA== X-Gm-Message-State: ALoCoQm/X2oOVCdlAAeH1eBNaEn0T5+kWK9qt5ZkZxcoBJvXMq2UFUQz57N5P/sOtc53TGukQ+nWK06BJg6ozv8iBMl5mAN0dooEMXVySZjeO4tViDqaEiI2ZEZokC9cBoja3hItVPBqsdYPA/5WZqWu0EJnEOw0kgVIiqCUBzcSof6xrCiZGQaQwvzr68UzGwS+v2CkAvnr2LM9CgS3USieGB31iprGfw== X-Received: by 10.68.170.131 with SMTP id am3mr40322454pbc.97.1398118644782; Mon, 21 Apr 2014 15:17:24 -0700 (PDT) Received: from localhost ([172.19.249.240]) by mx.google.com with ESMTPSA id zv3sm191922098pab.20.2014.04.21.15.17.22 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 21 Apr 2014 15:17:24 -0700 (PDT) Subject: [PATCH 2] PNP: Work around BIOS defects in Intel MCH area reporting To: "Rafael J. Wysocki" From: Bjorn Helgaas Cc: Aaron Lu , linux-pci@vger.kernel.org, x86@kernel.org, linux-kernel@vger.kernel.org, Stephane Eranian , linux-acpi@vger.kernel.org, Borislav Petkov , "H. Peter Anvin" , Zheng Z Yan , Dave Jones , Rui Zhang , Yinghai Lu Date: Mon, 21 Apr 2014 16:17:21 -0600 Message-ID: <20140421221721.26308.1891.stgit@bhelgaas-glaptop.roam.corp.google.com> User-Agent: StGit/0.16 MIME-Version: 1.0 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Work around BIOSes that don't report the entire Intel MCH area. MCHBAR is not an architected PCI BAR, so MCH space is usually reported as a PNP0C02 resource. The MCH space was once 16KB, but is 32KB in newer parts. Some BIOSes still report a PNP0C02 resource that is only 16KB, which means the rest of the MCH space is consumed but unreported. This can cause resource map sanity check warnings or (theoretically) a device conflict if we assigned the unreported space to another device. The Intel perf event uncore driver tripped over this when it claimed the MCH region: resource map sanity check conflict: 0xfed10000 0xfed15fff 0xfed10000 0xfed13fff pnp 00:01 Info: mapping multiple BARs. Your kernel is fine. To prevent this, if we find a PNP0C02 resource that covers part of the MCH space, extend it to cover the entire space. Link: http://lkml.kernel.org/r/20140224162400.GE16457@pd.tnic Reported-by: Borislav Petkov Tested-by: Borislav Petkov Signed-off-by: Bjorn Helgaas Acked-by: Borislav Petkov Acked-by: Stephane Eranian --- drivers/pnp/quirks.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pnp/quirks.c b/drivers/pnp/quirks.c index 258fef272ea7..0d679068ef1b 100644 --- a/drivers/pnp/quirks.c +++ b/drivers/pnp/quirks.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -334,6 +335,79 @@ static void quirk_amd_mmconfig_area(struct pnp_dev *dev) } #endif +/* Device IDs of parts that have 32KB MCH space */ +static const unsigned int mch_quirk_devices[] = { + 0x0154, /* Ivy Bridge */ + 0x0c00, /* Haswell */ +}; + +static struct pci_dev *get_intel_host(void) +{ + int i; + struct pci_dev *host; + + for (i = 0; i < ARRAY_SIZE(mch_quirk_devices); i++) { + host = pci_get_device(PCI_VENDOR_ID_INTEL, mch_quirk_devices[i], + NULL); + if (host) + return host; + } + return NULL; +} + +static void quirk_intel_mch(struct pnp_dev *dev) +{ + struct pci_dev *host; + u32 addr_lo, addr_hi; + struct pci_bus_region region; + struct resource mch; + struct pnp_resource *pnp_res; + struct resource *res; + + host = get_intel_host(); + if (!host) + return; + + /* + * MCHBAR is not an architected PCI BAR, so MCH space is usually + * reported as a PNP0C02 resource. The MCH space was originally + * 16KB, but is 32KB in newer parts. Some BIOSes still report a + * PNP0C02 resource that is only 16KB, which means the rest of the + * MCH space is consumed but unreported. + */ + + /* + * Read MCHBAR for Host Member Mapped Register Range Base + * https://www-ssl.intel.com/content/www/us/en/processors/core/4th-gen-core-family-desktop-vol-2-datasheet + * Sec 3.1.12. + */ + pci_read_config_dword(host, 0x48, &addr_lo); + region.start = addr_lo & ~0x7fff; + pci_read_config_dword(host, 0x4c, &addr_hi); + region.start |= (u64) addr_hi << 32; + region.end = region.start + 32*1024 - 1; + + memset(&mch, 0, sizeof(mch)); + mch.flags = IORESOURCE_MEM; + pcibios_bus_to_resource(host->bus, &mch, ®ion); + + list_for_each_entry(pnp_res, &dev->resources, list) { + res = &pnp_res->res; + if (res->end < mch.start || res->start > mch.end) + continue; /* no overlap */ + if (res->start == mch.start && res->end == mch.end) + continue; /* exact match */ + + dev_info(&dev->dev, FW_BUG "PNP resource %pR covers only part of %s Intel MCH; extending to %pR\n", + res, pci_name(host), &mch); + res->start = mch.start; + res->end = mch.end; + break; + } + + pci_dev_put(host); +} + /* * PnP Quirks * Cards or devices that need some tweaking due to incomplete resource info @@ -364,6 +438,7 @@ static struct pnp_fixup pnp_fixups[] = { #ifdef CONFIG_AMD_NB {"PNP0c01", quirk_amd_mmconfig_area}, #endif + {"PNP0c02", quirk_intel_mch}, {""} };