From patchwork Thu Nov 17 14:30:06 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 9434321 X-Patchwork-Delegate: rjw@sisk.pl Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5ACD560238 for ; Thu, 17 Nov 2016 14:30:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4CAA829544 for ; Thu, 17 Nov 2016 14:30:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 415DF29571; Thu, 17 Nov 2016 14:30:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C6D5929544 for ; Thu, 17 Nov 2016 14:30:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754069AbcKQOaf (ORCPT ); Thu, 17 Nov 2016 09:30:35 -0500 Received: from mga03.intel.com ([134.134.136.65]:50970 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753435AbcKQOae (ORCPT ); Thu, 17 Nov 2016 09:30:34 -0500 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP; 17 Nov 2016 06:30:09 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,506,1473145200"; d="scan'208";a="5571714" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga002.jf.intel.com with ESMTP; 17 Nov 2016 06:30:08 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id 6D87D30D; Thu, 17 Nov 2016 16:30:07 +0200 (EET) From: Andy Shevchenko To: linux-acpi@vger.kernel.org, "Rafael J . Wysocki" , mika.westerberg@linux.intel.com Cc: Andy Shevchenko Subject: [PATCH v2 1/1] ACPI / LPSS: enable hard LLP for DMA Date: Thu, 17 Nov 2016 16:30:06 +0200 Message-Id: <20161117143006.130266-1-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.10.2 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Right now the DMA support of hard LLP (*) is fused. Enable it via specific message sent to SoC at run time. (*) Hard LLP stands for the multi-block transfer feature of DMA controller supported by hardware. Tested-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- In v2: - massage commit message - add Mika's tag drivers/acpi/acpi_lpss.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/acpi/acpi_lpss.c b/drivers/acpi/acpi_lpss.c index 373657f..8ea836c 100644 --- a/drivers/acpi/acpi_lpss.c +++ b/drivers/acpi/acpi_lpss.c @@ -718,13 +718,14 @@ static int acpi_lpss_resume_early(struct device *dev) #define LPSS_GPIODEF0_DMA1_D3 BIT(2) #define LPSS_GPIODEF0_DMA2_D3 BIT(3) #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2) +#define LPSS_GPIODEF0_DMA_LLP BIT(13) static DEFINE_MUTEX(lpss_iosf_mutex); static void lpss_iosf_enter_d3_state(void) { u32 value1 = 0; - u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK; + u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; u32 value2 = LPSS_PMCSR_D3hot; u32 mask2 = LPSS_PMCSR_Dx_MASK; /* @@ -768,8 +769,9 @@ static void lpss_iosf_enter_d3_state(void) static void lpss_iosf_exit_d3_state(void) { - u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3; - u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK; + u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 | + LPSS_GPIODEF0_DMA_LLP; + u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; u32 value2 = LPSS_PMCSR_D0; u32 mask2 = LPSS_PMCSR_Dx_MASK;