From patchwork Tue Feb 14 23:53:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christopher Covington X-Patchwork-Id: 9573065 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 45BFE601E7 for ; Tue, 14 Feb 2017 23:54:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 37F2C28418 for ; Tue, 14 Feb 2017 23:54:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2666D2842B; Tue, 14 Feb 2017 23:54:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5CD7028418 for ; Tue, 14 Feb 2017 23:54:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750930AbdBNXyW (ORCPT ); Tue, 14 Feb 2017 18:54:22 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:54602 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750791AbdBNXyU (ORCPT ); Tue, 14 Feb 2017 18:54:20 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id A0E6660D62; Tue, 14 Feb 2017 23:54:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1487116459; bh=VwSavphWcJeCpMHjzsTlDU2Ug9S6uVsIaCAnNr+ewAw=; h=From:To:Cc:Subject:Date:From; b=oPUe//mYiV5okRl0/ysmHy2nL0shindX5XC0EqEtQoxuH1sh9J5J7c8gfkalwO1Sc yYclAwfqpp2JcGnsccx0nwOF0gpSzNEjhoyWdnI7B3W9DS/+wsrME2XI7sg2VHmz1o yZj/oJPGHJWWWH3EFzp1Ttb1EB/Ep1Z5ZOqUYPPI= Received: from illium.qualcomm.com (global_nat1_iad_fw.qualcomm.com [129.46.232.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: cov@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 77E38601A1; Tue, 14 Feb 2017 23:54:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1487116457; bh=VwSavphWcJeCpMHjzsTlDU2Ug9S6uVsIaCAnNr+ewAw=; h=From:To:Cc:Subject:Date:From; b=iVDudVi+gN945AkZvOYtcZpAbuEQGGlVSbrvnqzuPNty3LzMeEeM2xlRBNBjrZJC1 sfiX9s4DtZhdhip45sD4VHdH6drc3ezWThVN70MEuw/mBl2mtj091WcwBbRt3BCBCw 8dKme7xEbuA7K88Dcfs2eB6IBDaKS6RrBtj/lu9E= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 77E38601A1 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=cov@codeaurora.org From: Christopher Covington To: Jonathan Corbet , Marc Zyngier , Catalin Marinas , Will Deacon , linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mark Rutland , Peter Hurley , Aleksey Makarov , Robin Murphy , linux-kernel@vger.kernel.org, shankerd@codeaurora.org, timur@codeaurora.org, "Rafael J. Wysocki" , Len Brown , Russell King , Greg Kroah-Hartman , Jiri Slaby , linux-acpi@vger.kernel.org, linux-serial@vger.kernel.org Cc: Mark Langsdorf , Mark Salter , Jon Masters , Neil Leeder , Christopher Covington Subject: [PATCH v2] tty: pl011: Work around QDF2400 E44 stuck BUSY bit Date: Tue, 14 Feb 2017 18:53:47 -0500 Message-Id: <20170214235347.8812-1-cov@codeaurora.org> X-Mailer: git-send-email 2.9.3 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Qualcomm Datacenter Technologies QDF2400 family of SoCs contains a custom (non-PrimeCell) implementation of the SBSA UART. Occasionally the BUSY bit in the Flag Register gets stuck as 1, erratum 44 for both 2432v1 and 2400v1 SoCs. Checking that the Transmit FIFO Empty (TXFE) bit is 0, instead of checking that the BUSY bit is 1, works around the issue. To facilitate this substitution when UART AMBA Port (UAP) data is available, introduce vendor-specific inversion of Feature Register bits. For the earlycon case, implement alternative putc and early_write functions. Similar to what how ARMv8 ACPI PCI quirks are detected during MCFG parsing, check the OEM fields of the Serial Port Console Redirection (SPCR) ACPI table to determine if the current platform is known to be affected by the erratum. Signed-off-by: Christopher Covington Acked-by: Russell King Acked-by: Mark Rutland --- Changes in v2: * Improved comments per Timur * Removed #ifdef CONFIG_QCOM_QDF2400_ERRATUM_44 per Robin * Moved from MIDR based affected system detection to ACPI based per Mark and Robin * Combined earlycon and UAP-available workarounds back into one patch * Keeping Russell's Acked-by because I don't think I've drastically changed the PL011 bits, but please let me know if I'm wrong * Happy Valentine's Day! --- Documentation/arm64/silicon-errata.txt | 2 + drivers/acpi/spcr.c | 8 ++++ drivers/tty/serial/amba-pl011.c | 67 ++++++++++++++++++++++++++++++---- 3 files changed, 70 insertions(+), 7 deletions(-) diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index a71b8095dbd8..bc3d086bc624 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -68,3 +68,5 @@ stable kernels. | | | | | | Qualcomm Tech. | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 | | Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 | +| Qualcomm Tech. | QDF2432v1 UART | SoC E44 | N/A | +| Qualcomm Tech. | QDF2400v1 UART | SoC E44 | N/A | diff --git a/drivers/acpi/spcr.c b/drivers/acpi/spcr.c index b8019c4c1d38..59064f10353f 100644 --- a/drivers/acpi/spcr.c +++ b/drivers/acpi/spcr.c @@ -93,6 +93,14 @@ int __init parse_spcr(bool earlycon) goto done; } + if (!memcmp(table->header.oem_id, "QCOM ", ACPI_OEM_ID_SIZE)) + if (!memcmp(table->header.oem_table_id, "QDF2432 ", + ACPI_OEM_TABLE_ID_SIZE) || + (!memcmp(table->header.oem_table_id, + "QDF2400 ", ACPI_OEM_TABLE_ID_SIZE) && + table->header.oem_revision == 0)) + uart = "qdf2400_e44"; + snprintf(opts, sizeof(opts), "%s,%s,0x%llx,%d", uart, iotype, table->serial_port.address, baud_rate); diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c index d4171d71a258..4208012d52b2 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -97,6 +97,7 @@ struct vendor_data { unsigned int fr_dsr; unsigned int fr_cts; unsigned int fr_ri; + unsigned int inv_fr; bool access_32b; bool oversampling; bool dma_threshold; @@ -141,6 +142,30 @@ static struct vendor_data vendor_sbsa = { .fixed_options = true, }; +/* + * Erratum 44 for QDF2432v1 and QDF2400v1 SoCs describes the BUSY bit as + * occasionally getting stuck as 1. To avoid the potential for a hang, check + * TXFE == 0 instead of BUSY == 1. This may not be suitable for all UART + * implementations, so only do so if an affected platform is detected in + * parse_spcr(). + */ +static bool qdf2400_e44 = false; + +static struct vendor_data vendor_qdt_qdf2400_e44 = { + .reg_offset = pl011_std_offsets, + .fr_busy = UART011_FR_TXFE, + .fr_dsr = UART01x_FR_DSR, + .fr_cts = UART01x_FR_CTS, + .fr_ri = UART011_FR_RI, + .inv_fr = UART011_FR_TXFE, + .access_32b = true, + .oversampling = false, + .dma_threshold = false, + .cts_event_workaround = false, + .always_enabled = true, + .fixed_options = true, +}; + static u16 pl011_st_offsets[REG_ARRAY_SIZE] = { [REG_DR] = UART01x_DR, [REG_ST_DMAWM] = ST_UART011_DMAWM, @@ -1518,7 +1543,8 @@ static unsigned int pl011_tx_empty(struct uart_port *port) { struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port); - unsigned int status = pl011_read(uap, REG_FR); + /* Allow feature register bits to be inverted to work around errata */ + unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr; return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; } @@ -2215,10 +2241,12 @@ pl011_console_write(struct console *co, const char *s, unsigned int count) uart_console_write(&uap->port, s, count, pl011_console_putchar); /* - * Finally, wait for transmitter to become empty - * and restore the TCR + * Finally, wait for transmitter to become empty and restore the + * TCR. Allow feature register bits to be inverted to work around + * errata. */ - while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy) + while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr) + & uap->vendor->fr_busy) cpu_relax(); if (!uap->vendor->always_enabled) pl011_write(old_cr, uap, REG_CR); @@ -2340,8 +2368,13 @@ static int __init pl011_console_match(struct console *co, char *name, int idx, resource_size_t addr; int i; - if (strcmp(name, "pl011") != 0) + if (strcmp(name, "qdf2400_e44") == 0) { + if (!qdf2400_e44) + pr_info("UART: Working around QDF2400 SoC erratum 44"); + qdf2400_e44 = true; + } else if (strcmp(name, "pl011") != 0) { return -ENODEV; + } if (uart_parse_earlycon(options, &iotype, &addr, &options)) return -ENODEV; @@ -2383,6 +2416,25 @@ static struct console amba_console = { #define AMBA_CONSOLE (&amba_console) +static void qdf2400_e44_putc(struct uart_port *port, int c) +{ + while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) + cpu_relax(); + if (port->iotype == UPIO_MEM32) + writel(c, port->membase + UART01x_DR); + else + writeb(c, port->membase + UART01x_DR); + while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE)) + cpu_relax(); +} + +static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned n) +{ + struct earlycon_device *dev = con->data; + + uart_console_write(&dev->port, s, n, qdf2400_e44_putc); +} + static void pl011_putc(struct uart_port *port, int c) { while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) @@ -2408,7 +2460,8 @@ static int __init pl011_early_console_setup(struct earlycon_device *device, if (!device->port.membase) return -ENODEV; - device->con->write = pl011_early_write; + device->con->write = qdf2400_e44 ? + qdf2400_e44_early_write : pl011_early_write; return 0; } OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); @@ -2645,7 +2698,7 @@ static int sbsa_uart_probe(struct platform_device *pdev) uap->port.irq = ret; uap->reg_offset = vendor_sbsa.reg_offset; - uap->vendor = &vendor_sbsa; + uap->vendor = qdf2400_e44 ? &vendor_qdt_qdf2400_e44 : &vendor_sbsa; uap->fifosize = 32; uap->port.iotype = vendor_sbsa.access_32b ? UPIO_MEM32 : UPIO_MEM; uap->port.ops = &sbsa_uart_pops;