From patchwork Thu Dec 14 11:47:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Pieralisi X-Patchwork-Id: 10111905 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B6CF460327 for ; Thu, 14 Dec 2017 11:48:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A624829C18 for ; Thu, 14 Dec 2017 11:48:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9A9AB29C27; Thu, 14 Dec 2017 11:48:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EDB7929C18 for ; Thu, 14 Dec 2017 11:48:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752204AbdLNLsJ (ORCPT ); Thu, 14 Dec 2017 06:48:09 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:40402 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752026AbdLNLsI (ORCPT ); Thu, 14 Dec 2017 06:48:08 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 97C061529; Thu, 14 Dec 2017 03:48:07 -0800 (PST) Received: from e107981-ln.cambridge.arm.com (e107981-ln.cambridge.arm.com [10.1.207.54]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 609183F4FF; Thu, 14 Dec 2017 03:48:05 -0800 (PST) Date: Thu, 14 Dec 2017 11:47:59 +0000 From: Lorenzo Pieralisi To: Shameer Kolothum Cc: robin.murphy@arm.com, marc.zyngier@arm.com, will.deacon@arm.com, joro@8bytes.org, john.garry@huawei.com, xuwei5@hisilicon.com, guohanjun@huawei.com, iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, devicetree@vger.kernel.org, linuxarm@huawei.com Subject: Re: [PATCH v11 1/3] ACPI/IORT: Add msi address regions reservation helper Message-ID: <20171214114759.GA27117@e107981-ln.cambridge.arm.com> References: <20171213115830.61872-1-shameerali.kolothum.thodi@huawei.com> <20171213115830.61872-2-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20171213115830.61872-2-shameerali.kolothum.thodi@huawei.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Wed, Dec 13, 2017 at 11:58:28AM +0000, Shameer Kolothum wrote: > On some platforms msi parent address regions have to be excluded from > normal IOVA allocation in that they are detected and decoded in a HW > specific way by system components and so they cannot be considered normal > IOVA address space. > > Add a helper function that retrieves ITS address regions - the msi > parent - through IORT device <-> ITS mappings and reserves it so that > these regions will not be translated by IOMMU and will be excluded from > IOVA allocations. The function checks for the smmu model number and > only applies the msi reservation if the platform requires it. > > Signed-off-by: Shameer Kolothum > --- > drivers/acpi/arm64/iort.c | 112 +++++++++++++++++++++++++++++++++++++-- > drivers/irqchip/irq-gic-v3-its.c | 3 +- > include/linux/acpi_iort.h | 7 ++- > 3 files changed, 117 insertions(+), 5 deletions(-) You need this additional hunk to make it compile on !CONFIG_IOMMU_API: -- >8 -- --- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index 3e0ce652c3e8..e2f7bddf5522 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -762,25 +762,6 @@ static int __maybe_unused __get_pci_rid(struct pci_dev *pdev, u16 alias, return 0; } -static __maybe_unused struct acpi_iort_node *iort_get_msi_resv_iommu( - struct device *dev) -{ - struct acpi_iort_node *iommu; - struct iommu_fwspec *fwspec = dev->iommu_fwspec; - - iommu = iort_get_iort_node(fwspec->iommu_fwnode); - - if (iommu && (iommu->type == ACPI_IORT_NODE_SMMU_V3)) { - struct acpi_iort_smmu_v3 *smmu; - - smmu = (struct acpi_iort_smmu_v3 *)iommu->node_data; - if (smmu->model == ACPI_IORT_SMMU_V3_HISILICON_HI161X) - return iommu; - } - - return NULL; -} - static int arm_smmu_iort_xlate(struct device *dev, u32 streamid, struct fwnode_handle *fwnode, const struct iommu_ops *ops) @@ -807,6 +788,24 @@ static inline bool iort_iommu_driver_enabled(u8 type) } #ifdef CONFIG_IOMMU_API +static struct acpi_iort_node *iort_get_msi_resv_iommu(struct device *dev) +{ + struct acpi_iort_node *iommu; + struct iommu_fwspec *fwspec = dev->iommu_fwspec; + + iommu = iort_get_iort_node(fwspec->iommu_fwnode); + + if (iommu && (iommu->type == ACPI_IORT_NODE_SMMU_V3)) { + struct acpi_iort_smmu_v3 *smmu; + + smmu = (struct acpi_iort_smmu_v3 *)iommu->node_data; + if (smmu->model == ACPI_IORT_SMMU_V3_HISILICON_HI161X) + return iommu; + } + + return NULL; +} + static inline const struct iommu_ops *iort_fwspec_iommu_ops( struct iommu_fwspec *fwspec) {