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Tue, 29 Aug 2023 19:28:32 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D7.mail.protection.outlook.com (10.167.241.78) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6745.16 via Frontend Transport; Tue, 29 Aug 2023 19:28:32 +0000 Received: from AUS-P9-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 29 Aug 2023 14:28:31 -0500 From: Mario Limonciello To: , , , CC: , , , Mario Limonciello , Iain Lane Subject: [PATCH v16 3/3] platform/x86/amd: pmc: Don't let PCIe root ports go into D3 Date: Tue, 29 Aug 2023 12:12:12 -0500 Message-ID: <20230829171212.156688-4-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230829171212.156688-1-mario.limonciello@amd.com> References: <20230829171212.156688-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D7:EE_|DS7PR12MB6335:EE_ X-MS-Office365-Filtering-Correlation-Id: b3e8c513-e6ad-4752-5252-08dba8c621e4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Aug 2023 19:28:32.7565 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b3e8c513-e6ad-4752-5252-08dba8c621e4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D7.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6335 Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org commit 9d26d3a8f1b0 ("PCI: Put PCIe ports into D3 during suspend") changed pci_bridge_d3_possible() so that any vendor's PCIe ports from modern machines (>=2015) are allowed to be put into D3. Iain reports that USB devices can't be used to wake a Lenovo Z13 from suspend. This is because the PCIe root port has been put into D3 and AMD's platform can't handle USB devices waking from a hardware sleep state in this case. This problem only occurs on Linux, and only when the AMD PMC driver is utilized to put the device into a hardware sleep state. Comparing the behavior on Windows and Linux, Windows doesn't put the root ports into D3. A variety of approaches were discussed to change PCI core to handle this case generically but no consensus was reached. To limit the scope of effect only to the affected machines introduce a workaround into the amd-pmc driver to only apply to the PCI root ports in affected machines when going into hardware sleep. Link: https://lore.kernel.org/linux-pci/20230818193932.27187-1-mario.limonciello@amd.com/ Fixes: 9d26d3a8f1b0 ("PCI: Put PCIe ports into D3 during suspend") Reported-by: Iain Lane Closes: https://forums.lenovo.com/t5/Ubuntu/Z13-can-t-resume-from-suspend-with-external-USB-keyboard/m-p/5217121 Signed-off-by: Mario Limonciello Acked-by: Shyam Sundar S K --- v15->v16: * Only match PCIe root ports with ACPI companions * Use constraints when workaround activated --- drivers/platform/x86/amd/pmc/pmc.c | 39 ++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/platform/x86/amd/pmc/pmc.c index eb2a4263814c..6a037447ec5a 100644 --- a/drivers/platform/x86/amd/pmc/pmc.c +++ b/drivers/platform/x86/amd/pmc/pmc.c @@ -741,6 +741,41 @@ static int amd_pmc_czn_wa_irq1(struct amd_pmc_dev *pdev) return 0; } +/* only allow PCIe root ports with a LPS0 constraint configured to go to D3 */ +static int amd_pmc_rp_wa(struct amd_pmc_dev *pdev) +{ + struct pci_dev *pci_dev = NULL; + + while ((pci_dev = pci_get_device(PCI_VENDOR_ID_AMD, PCI_ANY_ID, pci_dev))) { + struct acpi_device *adev; + int constraint; + + if (!pci_is_pcie(pci_dev) || + !(pci_pcie_type(pci_dev) == PCI_EXP_TYPE_ROOT_PORT)) + continue; + + if (pci_dev->current_state == PCI_D3hot || + pci_dev->current_state == PCI_D3cold) + continue; + + adev = ACPI_COMPANION(&pci_dev->dev); + if (!adev) + continue; + + constraint = acpi_get_lps0_constraint(adev); + if (constraint != ACPI_STATE_UNKNOWN && + constraint >= ACPI_STATE_S3) + continue; + + if (pci_dev->bridge_d3 == 0) + continue; + pci_dev->bridge_d3 = 0; + dev_info(&pci_dev->dev, "Disabling D3 on PCIe root port due lack of constraint\n"); + } + + return 0; +} + static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg) { struct rtc_device *rtc_device; @@ -893,6 +928,10 @@ static int amd_pmc_suspend_handler(struct device *dev) case AMD_CPU_ID_CZN: rc = amd_pmc_czn_wa_irq1(pdev); break; + case AMD_CPU_ID_YC: + case AMD_CPU_ID_PS: + rc = amd_pmc_rp_wa(pdev); + break; default: break; }