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AJvYcCVMfrqzM4uZFwcdk3Oe1h3c0KCeWySD9V/ulA0O5WRz9H3DXDnIiPuYXpEyGHmSd9w4jX9gSUD/zhy+J0WHAx018V9aznYe9RkRLQ== X-Gm-Message-State: AOJu0Yz92dQZLD+FiO1JvRedtjouWBXXgwpszBv2gy876ngWg0VB+3/D IQhpqzpRpydKuXSCjanY1kE7pkjeVdiHf61Rpy1i40T2VTEVLX1CGynPXmUdHFc= X-Google-Smtp-Source: AGHT+IG/D+4lV51kE6nf+1RISOvQK/tQQrWPzktPgLKIYfH6V7gZRVDpOTsPNQO9YGcb3oeKoFgoIg== X-Received: by 2002:a17:903:258f:b0:1ed:1d37:267e with SMTP id d9443c01a7336-1eeb05919damr43288965ad.16.1715240038702; Thu, 09 May 2024 00:33:58 -0700 (PDT) Received: from L6YN4KR4K9.bytedance.net ([61.213.176.14]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ef0badcbacsm7519045ad.97.2024.05.09.00.33.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 09 May 2024 00:33:58 -0700 (PDT) From: Yunhui Cui To: rafael@kernel.org, lenb@kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, sunilvl@ventanamicro.com, aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org, bhelgaas@google.com, james.morse@arm.com, jhugo@codeaurora.org, jeremy.linton@arm.com, john.garry@huawei.com, Jonathan.Cameron@huawei.com, pierre.gondois@arm.com, sudeep.holla@arm.com, tiantao6@huawei.com Cc: Yunhui Cui , Conor Dooley Subject: [PATCH v5 2/3] riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT Date: Thu, 9 May 2024 15:32:59 +0800 Message-Id: <20240509073300.4968-2-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20240509073300.4968-1-cuiyunhui@bytedance.com> References: <20240509073300.4968-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Before cacheinfo can be built correctly, we need to initialize level and type. Since RISC-V currently does not have a register group that describes cache-related attributes like ARM64, we cannot obtain them directly, so now we obtain cache leaves from the ACPI PPTT table (acpi_get_cache_info()) and set the cache type through split_levels. Suggested-by: Jeremy Linton Suggested-by: Sudeep Holla Reviewed-by: Conor Dooley Reviewed-by: Sunil V L Signed-off-by: Yunhui Cui Reviewed-by: Jeremy Linton --- arch/riscv/kernel/cacheinfo.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c index 30a6878287ad..d6c108c50cba 100644 --- a/arch/riscv/kernel/cacheinfo.c +++ b/arch/riscv/kernel/cacheinfo.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 SiFive */ +#include #include #include #include @@ -78,6 +79,27 @@ int populate_cache_leaves(unsigned int cpu) struct device_node *prev = NULL; int levels = 1, level = 1; + if (!acpi_disabled) { + int ret, fw_levels, split_levels; + + ret = acpi_get_cache_info(cpu, &fw_levels, &split_levels); + if (ret) + return ret; + + BUG_ON((split_levels > fw_levels) || + (split_levels + fw_levels > this_cpu_ci->num_leaves)); + + for (; level <= this_cpu_ci->num_levels; level++) { + if (level <= split_levels) { + ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); + ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); + } else { + ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); + } + } + return 0; + } + if (of_property_read_bool(np, "cache-size")) ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); if (of_property_read_bool(np, "i-cache-size"))