From patchwork Mon Aug 12 00:59:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 13759944 Received: from mail-oi1-f176.google.com (mail-oi1-f176.google.com [209.85.167.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57519535D8 for ; Mon, 12 Aug 2024 01:01:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723424471; cv=none; b=BLlTSsiNMZNHWPV6/UvHUwHFaiXcuJs/zwe+PuEfMuCWnqeMbKxnxX4+Se+i3jG1XRoD58jqBTAujIW4cmoad1sZXg5OQRBgIVJomx+Q5aw1iImtmKLIlyqwwDeA2SinyzR1SeF5k2Pfx07z7AzOQbjtdq14a/x6JMV3qmrNu6o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723424471; c=relaxed/simple; bh=kUGmilJtSEYHecokfsz1Dv8H4HmvP4hekzWOib2uw/4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dXhb20SvWQ8wCh52kud9jB2FUcgSMocymYyVXGmxisLt8lYv/hMyD4zOmvqTZkIWns5CYN1N1JZdH1JHDftkS1fa3NJGrdb9xkcYT1Xfs2zI+ZOt4xbmvfZ2Y4HiZWGlhAtr/M+r6uREdaSrOBAN02Ltf8GtteOheVq9Kx752Cc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=kWYK6Fq/; arc=none smtp.client-ip=209.85.167.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="kWYK6Fq/" Received: by mail-oi1-f176.google.com with SMTP id 5614622812f47-3dab336717fso2632602b6e.0 for ; Sun, 11 Aug 2024 18:01:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1723424469; x=1724029269; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=L2F9HlOmYYBgfOGZ5Y5XAW+7ZHo7CSZJxIOIoseG4Ek=; b=kWYK6Fq/HwdwMPdSnaD01bOjKw/O3sxBsSzc06M8JflmeLCiw8H2wVKZUrovQGpVJX EvYk47MD/ieoRgy60gt2rTOGt4lKlZJ9u3Gd81wgmKf/lwLf+OePaorIjOOJsTfViZ5q dS4LX5DgvX+qlI91hDr7yz5nya1JUYpSfOO2puRfodzSWthO4CiKL/oztDEneEo+LOEo A3fKPwRDUXTMuMXw0H/slEJPCSA3C3WTrbgEfpnBPhztFp+xE/GnghQvmkpxLtIFN9tS 1NubejwkX+KR1eaTead5IhTRpuYfmqklZKf52QEHs2x/lJsJWiJ+Mw3quCVE1FUejdu3 eQfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1723424469; x=1724029269; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L2F9HlOmYYBgfOGZ5Y5XAW+7ZHo7CSZJxIOIoseG4Ek=; b=jaF8kPstQNAxwSr6GN6Zs/ZSH7lYUxF7owtv0wZRX9ui+GSFeeViXjmZL+DRJ2xw+w szIPlN/sdqAX21SiBcXYnMu96HxcvXqelp7tykK4RnvxlKFcegENe1vU9TqXDZQUocsg yHI25NnO5yOCkq79+turHC+iobKOCVWMN6fhRVx4wfiprq2xv5jEWxQdTToWvpG2b24Z 6zf6O3qJpIWD0UR6uRlL+JKLrOz7bkJuYCvQWbMhCkUyHeZuhz6olOf+v1+m4S36gPI2 KHJFuVA23h18y8/U/bYtceVltzReDuUR/aaRB0pTVSmOujMGnv/LAE67LsINYDgYkKnI NEvg== X-Forwarded-Encrypted: i=1; AJvYcCVKwoYY0urjKLK+f1ISQv7r1BpE++6YNmAwM2/wSJ2kCkuJBGNGXRHOukOj8GcEgL7QL2LYeKjfvtaznGTzGm6zPesoMrFxceF5jA== X-Gm-Message-State: AOJu0YzyJI2aVA4Rzl8ouxNkglg1s2o0G7bB5Xl0+DlKrauMi7i5vqSr AMaV3nA9wx1kzvUaCn/UCkozIwWTlp5npVqLAb6LFKXm6IVMPhgbdEIJp1v+ksc= X-Google-Smtp-Source: AGHT+IHZXV1nZ3pGHtKOzIjfGzSIJM5PQQnjoEr5t/Q7EAetVkMKeElEktJkKAiBNFFJkWIu7MYWBg== X-Received: by 2002:a05:6808:bcc:b0:3d9:35df:8f2 with SMTP id 5614622812f47-3dc4169de4bmr11444935b6e.28.1723424469384; Sun, 11 Aug 2024 18:01:09 -0700 (PDT) Received: from sunil-pc.tail07344b.ts.net ([106.51.198.16]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7c3dbe8cbdcsm3074062a12.61.2024.08.11.18.01.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Aug 2024 18:01:08 -0700 (PDT) From: Sunil V L To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev Cc: Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Samuel Holland , Robert Moore , Conor Dooley , Haibo Xu , Andrew Jones , Atish Kumar Patra , Drew Fustini , Sunil V L , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= Subject: [PATCH v8 14/17] irqchip/riscv-imsic-state: Create separate function for DT Date: Mon, 12 Aug 2024 06:29:26 +0530 Message-ID: <20240812005929.113499-15-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240812005929.113499-1-sunilvl@ventanamicro.com> References: <20240812005929.113499-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 While populating IMSIC global structure, many fields are initialized using DT properties. Make the code which uses DT properties as separate function so that it is easier to add ACPI support later. No functionality added/changed. Suggested-by: Thomas Gleixner Signed-off-by: Sunil V L Reviewed-by: Anup Patel Tested-by: Björn Töpel --- drivers/irqchip/irq-riscv-imsic-state.c | 97 ++++++++++++++----------- 1 file changed, 55 insertions(+), 42 deletions(-) diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-riscv-imsic-state.c index 5479f872e62b..f9e70832863a 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.c +++ b/drivers/irqchip/irq-riscv-imsic-state.c @@ -510,6 +510,60 @@ static int __init imsic_matrix_init(void) return 0; } +static int __init imsic_populate_global_dt(struct fwnode_handle *fwnode, + struct imsic_global_config *global, + u32 *nr_parent_irqs) +{ + int rc; + + /* Find number of guest index bits in MSI address */ + rc = of_property_read_u32(to_of_node(fwnode), "riscv,guest-index-bits", + &global->guest_index_bits); + if (rc) + global->guest_index_bits = 0; + + /* Find number of HART index bits */ + rc = of_property_read_u32(to_of_node(fwnode), "riscv,hart-index-bits", + &global->hart_index_bits); + if (rc) { + /* Assume default value */ + global->hart_index_bits = __fls(*nr_parent_irqs); + if (BIT(global->hart_index_bits) < *nr_parent_irqs) + global->hart_index_bits++; + } + + /* Find number of group index bits */ + rc = of_property_read_u32(to_of_node(fwnode), "riscv,group-index-bits", + &global->group_index_bits); + if (rc) + global->group_index_bits = 0; + + /* + * Find first bit position of group index. + * If not specified assumed the default APLIC-IMSIC configuration. + */ + rc = of_property_read_u32(to_of_node(fwnode), "riscv,group-index-shift", + &global->group_index_shift); + if (rc) + global->group_index_shift = IMSIC_MMIO_PAGE_SHIFT * 2; + + /* Find number of interrupt identities */ + rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-ids", + &global->nr_ids); + if (rc) { + pr_err("%pfwP: number of interrupt identities not found\n", fwnode); + return rc; + } + + /* Find number of guest interrupt identities */ + rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-guest-ids", + &global->nr_guest_ids); + if (rc) + global->nr_guest_ids = global->nr_ids; + + return 0; +} + static int __init imsic_get_parent_hartid(struct fwnode_handle *fwnode, u32 index, unsigned long *hartid) { @@ -578,50 +632,9 @@ static int __init imsic_parse_fwnode(struct fwnode_handle *fwnode, return -EINVAL; } - /* Find number of guest index bits in MSI address */ - rc = of_property_read_u32(to_of_node(fwnode), "riscv,guest-index-bits", - &global->guest_index_bits); + rc = imsic_populate_global_dt(fwnode, global, nr_parent_irqs); if (rc) - global->guest_index_bits = 0; - - /* Find number of HART index bits */ - rc = of_property_read_u32(to_of_node(fwnode), "riscv,hart-index-bits", - &global->hart_index_bits); - if (rc) { - /* Assume default value */ - global->hart_index_bits = __fls(*nr_parent_irqs); - if (BIT(global->hart_index_bits) < *nr_parent_irqs) - global->hart_index_bits++; - } - - /* Find number of group index bits */ - rc = of_property_read_u32(to_of_node(fwnode), "riscv,group-index-bits", - &global->group_index_bits); - if (rc) - global->group_index_bits = 0; - - /* - * Find first bit position of group index. - * If not specified assumed the default APLIC-IMSIC configuration. - */ - rc = of_property_read_u32(to_of_node(fwnode), "riscv,group-index-shift", - &global->group_index_shift); - if (rc) - global->group_index_shift = IMSIC_MMIO_PAGE_SHIFT * 2; - - /* Find number of interrupt identities */ - rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-ids", - &global->nr_ids); - if (rc) { - pr_err("%pfwP: number of interrupt identities not found\n", fwnode); return rc; - } - - /* Find number of guest interrupt identities */ - rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-guest-ids", - &global->nr_guest_ids); - if (rc) - global->nr_guest_ids = global->nr_ids; /* Sanity check guest index bits */ i = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT;