From patchwork Wed Feb 19 18:41:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sohil Mehta X-Patchwork-Id: 13982757 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7277522B5B6; Wed, 19 Feb 2025 19:28:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739993317; cv=none; b=e2bVhgYCzgE2Ejj1rvEAosGdfvPE3Qsq8ouhLTYuAt5lG4UdnZOPHNIqcC5AfV2bK6kb+W1bD9RQOjb8lem+nCpBVXseMwuiWVrAeI0pJ9S64bFy1TxdurilGUn9v4QlCioUuxnMTH3CTZsaIi5upvY+hGVVl7X0PTE/3Q2YamM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739993317; c=relaxed/simple; bh=XcZCN0XcDsRlRdxcZACk+AqTvXZkPzdsqu3ONzEfFfw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GzQ/Yj7ltC5PLpV1SJuU7skZ71enL0zEbem6XsS/4h2/X/SFeDRZY8Pn/N2ME9vLQpct8ACWEgJwE2fAxLsg4fULm43yw+TUcs/1xO59uQIwhaQV66XfVdkySTqwGMf+tPsyOkrEfMQNjZecAT7ET6DSY2AQ5mRWG+34OVmklAo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=bDhRixsp; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="bDhRixsp" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739993315; x=1771529315; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XcZCN0XcDsRlRdxcZACk+AqTvXZkPzdsqu3ONzEfFfw=; b=bDhRixsp2uzQUjVRG/weU/2ACsHc6t1Itixxb8KxckWaKgTRCfGyTl+i dZw+jYdm2dsla7qpxkctRe3tUZqEpsuilvcQ5rnUPvvta4m20IWcGRbuN Gb+EeutfXyXFzNAC5PmViQL22b+Ao2Tqm4XHxEdZsnMIYIv3jSWDT6ldh wPfxv1xciMIFdphqBHvTIRnVEQvoRxk9AdtEvmpzI15sj92lNIciGP2bQ a70MB5dOjc8Hr4pl+1E9jAD86Oye19E8s0uveaqswcnH3yhURfYjW3Qb6 Z2OUoOFlPukLNoc+NOhsnVnqLftRfw0H+0KBsBYxP5KqA8No/5eJlaijZ A==; X-CSE-ConnectionGUID: WUNT1v7RRsCTv2a35lhKvg== X-CSE-MsgGUID: oEtZh6u+TGSV0vXPX96gEA== X-IronPort-AV: E=McAfee;i="6700,10204,11314"; a="52182791" X-IronPort-AV: E=Sophos;i="6.12,310,1728975600"; d="scan'208";a="52182791" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2025 11:28:33 -0800 X-CSE-ConnectionGUID: xvQ7NeXFRNi8UApQAnE6dg== X-CSE-MsgGUID: Eao1edzORxqeawS+xufnyQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,299,1732608000"; d="scan'208";a="115344008" Received: from sohilmeh.sc.intel.com ([172.25.103.65]) by fmviesa010.fm.intel.com with ESMTP; 19 Feb 2025 10:45:43 -0800 From: Sohil Mehta To: x86@kernel.org, Dave Hansen , Tony Luck Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Thomas Gleixner , Borislav Petkov , "H . Peter Anvin" , "Rafael J . Wysocki" , Len Brown , Andy Lutomirski , Viresh Kumar , Jean Delvare , Guenter Roeck , Zhang Rui , Andrew Cooper , David Laight , Dapeng Mi , Sohil Mehta , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v3 03/15] x86/microcode: Update the Intel processor flag scan check Date: Wed, 19 Feb 2025 18:41:21 +0000 Message-ID: <20250219184133.816753-4-sohil.mehta@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250219184133.816753-1-sohil.mehta@intel.com> References: <20250219184133.816753-1-sohil.mehta@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Family model check to read the processor flag MSR is misleading and potentially incorrect. It doesn't consider Family while comparing the model number. The original check did have a Family number but it got lost/moved during refactoring. intel_collect_cpu_info() is called through multiple paths such as early initialization, CPU hotplug as well as IFS image load. Some of these flows would be error prone due to the ambiguous check. Correct the processor flag scan check to use a Family number and update it to a VFM based one to make it more readable. Signed-off-by: Sohil Mehta Acked-by: Dave Hansen --- v3: Picked up Dave's Ack. v2: Use a VFM check instead of hardcoded numbers. --- arch/x86/include/asm/intel-family.h | 1 + arch/x86/kernel/cpu/microcode/intel.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index 6d7b04ffc5fd..cccc932d761e 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -46,6 +46,7 @@ #define INTEL_ANY IFM(X86_FAMILY_ANY, X86_MODEL_ANY) #define INTEL_PENTIUM_PRO IFM(6, 0x01) +#define INTEL_PENTIUM_III_DESCHUTES IFM(6, 0x05) #define INTEL_CORE_YONAH IFM(6, 0x0E) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index f3d534807d91..819199bc0119 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -74,7 +74,7 @@ void intel_collect_cpu_info(struct cpu_signature *sig) sig->pf = 0; sig->rev = intel_get_microcode_revision(); - if (x86_model(sig->sig) >= 5 || x86_family(sig->sig) > 6) { + if (IFM(x86_family(sig->sig), x86_model(sig->sig)) >= INTEL_PENTIUM_III_DESCHUTES) { unsigned int val[2]; /* get processor flags from MSR 0x17 */