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[v1,02/20] ACPICA: Complete CXL 3.0 CXIMS structures

Message ID 4925809.GXAFRqVoOG@rjwysocki.net (mailing list archive)
State In Next
Delegated to: Rafael Wysocki
Headers show
Series ACPICA: Release 20240827 | expand

Commit Message

Rafael J. Wysocki Aug. 29, 2024, 6:22 p.m. UTC 
From: Zhang Rui <rui.zhang@intel.com>

ACPICA commit eb2a2ff303416fb3f6c425d519dbcd6988dbd91f

Commit 2d8dc0383d3c9 ("Add CXL 3.0 structures (CXIMS & RDPAS) to the
CEDT table") introduces basic support for CXL XOR Interleave Math
Structure (CXIMS).

Complete the CXIMS structures.

No functional change.

Link: https://github.com/acpica/acpica/commit/eb2a2ff3
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 include/acpi/actbl1.h | 4 ++++
 1 file changed, 4 insertions(+)
diff mbox series

Patch

diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
index 841ef9f22795..8cfcd1e1c177 100644
--- a/include/acpi/actbl1.h
+++ b/include/acpi/actbl1.h
@@ -567,6 +567,10 @@  struct acpi_cedt_cxims {
 	u64 xormap_list[];
 };
 
+struct acpi_cedt_cxims_target_element {
+	u64 xormap;
+};
+
 /* 3: CXL RCEC Downstream Port Association Structure */
 
 struct acpi_cedt_rdpas {