From patchwork Wed Jul 28 04:35:32 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Len Brown X-Patchwork-Id: 114770 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o6SETwKE009142 for ; Wed, 28 Jul 2010 14:29:58 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754744Ab0G1O33 (ORCPT ); Wed, 28 Jul 2010 10:29:29 -0400 Received: from vms173009pub.verizon.net ([206.46.173.9]:56264 "EHLO vms173009pub.verizon.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754479Ab0G1O31 (ORCPT ); Wed, 28 Jul 2010 10:29:27 -0400 Received: from localhost.localdomain ([unknown] [64.140.212.33]) by vms173009.mailsrvcs.net (Sun Java(tm) System Messaging Server 7u2-7.02 32bit (built Apr 16 2009)) with ESMTPA id <0L69001EXUWL1K70@vms173009.mailsrvcs.net>; Wed, 28 Jul 2010 09:29:17 -0500 (CDT) Received: from localhost.localdomain (x980 [127.0.0.1]) by localhost.localdomain (8.14.4/8.14.4) with ESMTP id o6SET8RI002364; Wed, 28 Jul 2010 10:29:09 -0400 Received: from localhost (lenb@localhost) by localhost.localdomain (8.14.4/8.14.4/Submit) with ESMTP id o6S4ZW85025615; Wed, 28 Jul 2010 00:35:33 -0400 X-Authentication-warning: localhost.localdomain: lenb owned process doing -bs Date: Wed, 28 Jul 2010 00:35:32 -0400 (EDT) From: Len Brown X-X-Sender: lenb@localhost.localdomain To: x86@kernel.org Cc: Linux Kernel Mailing List , linux-acpi@vger.kernel.org, venki@google.com Subject: [PATCH 1/2] [PATCH] x86: Look for TSC Deadline Timer Message-id: User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-version: 1.0 Content-type: TEXT/PLAIN; charset=US-ASCII Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 28 Jul 2010 14:29:58 +0000 (UTC) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 4681459..b2a47e6 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -120,6 +120,7 @@ #define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */ #define X86_FEATURE_MOVBE (4*32+22) /* MOVBE instruction */ #define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */ +#define X86_FEATURE_TSC_DEADLINE (4*32+24) /* "tdt" TSC Deadline Timer */ #define X86_FEATURE_AES (4*32+25) /* AES instructions */ #define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ #define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 8c7ae43..78d0d5b 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -268,6 +268,8 @@ #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) +#define MSR_IA32_TSC_DEADLINE 0x000006E0 + /* P4/Xeon+ specific */ #define MSR_IA32_MCG_EAX 0x00000180 #define MSR_IA32_MCG_EBX 0x00000181