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[2003:dc:d716:e000:f8f1:a759:b0fa:a67f]) by smtp.googlemail.com with ESMTPSA id p64-v6sm1776483wrc.97.2018.09.27.01.59.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 27 Sep 2018 01:59:30 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, jbrunet@baylibre.com, narmstrong@baylibre.com Subject: [PATCH 0/2] Meson8b: fixes for the cpu_scale_div clock Date: Thu, 27 Sep 2018 10:59:19 +0200 Message-Id: <20180927085921.24627-1-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.19.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180927_015956_860847_33C69B6E X-CRM114-Status: GOOD ( 11.44 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: carlo@caione.org, Martin Blumenstingl , linux-clk@vger.kernel.org Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP While trying to add support for the TWD timer I found that our CPU clock calculation (when running off the "cpu_scale_div clock) is incorrect. The main problem was the cpu_scale_div clock: it's divider table has an off-by-one error. the old formula was: parent_rate / 2 * register_value however, testing shows that the correct formula is: parent_rate / 2 * (register value + 1) See the commit message of patch #1 for a complete description of the problem and it's history. While looking at the "cpu_scale_div" clock I also found that it's register width was also off-by-one, so this is fixed in a separate patch as well. Both patches are not critical because I haven't seen a case where u-boot uses cpu_scale_div for the CPU clock. It's only a problem when playing with the CPU clock in u-boot (by writing registers manually) or as soon as we support CPU frequency scaling. Martin Blumenstingl (2): clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_table clk: meson: meson8b: fix the width of the cpu_scale_div clock drivers/clk/meson/meson8b.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-)