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[2003:dc:d707:2200:6919:79d1:fb98:407]) by smtp.googlemail.com with ESMTPSA id 193-v6sm11699772wmj.21.2018.10.28.05.09.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 28 Oct 2018 05:09:06 -0700 (PDT) From: Martin Blumenstingl To: narmstrong@baylibre.com, jbrunet@baylibre.com, robh+dt@kernel.org, mark.rutland@arm.com, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v2 0/3] Meson8/Meson8b: introduce a HHI syscon node Date: Sun, 28 Oct 2018 13:08:56 +0100 Message-Id: <20181028120859.5735-1-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181028_050920_013900_FF8E37FE X-CRM114-Status: GOOD ( 12.21 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sboyd@kernel.org, khilman@baylibre.com, mturquette@baylibre.com, Martin Blumenstingl , carlo@caione.org, linux-clk@vger.kernel.org Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The Meson8/Meson8b/Meson8m2 SoCs are suffering from a similar problem as the GXBB/GXL/GXM SoCs (see the GX series from Jerome: [0]): There is a register area called "HHI" which is used for multiple IP blocks of the SoC: - the system clock controller - a few reset lines (there is a separate reset controller, these reset lines are not part of the other reset controller). this reset controller is currently implemented in the clock controller driver - a HDMI controller - temperature sensor calibration data (by "data" I really mean data, the ADC driver has four bits for the TSC data in it's own register space, however on Meson8b and Meson8m2 there is a fifth TSC bit which is stored in the HHI register area) The first three could be implemented with a single node (either in one big driver, or using a MFD driver which would register function- specific drivers). However, the TSC data is a big problem, because the ADC has it's own set of registers but needs to write one bit in the HHI register area. NOTE: this series has multiple dependencies: - the clock controller changes depend "meson8b: add the CPU_DIV16 clock for the ARM TWD" as well as "meson8b: register the clock controller early" [2] - the dts changes depend on "fix clock controller register size on Meson8/Meson8b" [3] Changes since v1 at [4]: - added a "amlogic,meson-hhi-sysctrl" compatible to the syscon node (which is the parent of the clock controller) in patch #1 and #3 - added Neil's Acked-by - rebased on top of clk-meson's meson-clk-4.20-1 tag and my other series "Meson8b: fixes for the cpu_scale_div clock" from [5] [0] http://lists.infradead.org/pipermail/linux-amlogic/2018-March/006733.html [1] http://lists.infradead.org/pipermail/linux-amlogic/2018-July/007890.html [2] http://lists.infradead.org/pipermail/linux-amlogic/2018-July/007900.html [3] http://lists.infradead.org/pipermail/linux-amlogic/2018-July/007897.html [4] https://patchwork.kernel.org/cover/10539051/ [5] https://patchwork.kernel.org/cover/10617617/ Martin Blumenstingl (3): dt-bindings: clock: meson8b: use the registers from the HHI syscon clk: meson: meson8b: use the HHI syscon if available ARM: dts: meson: switch the clock controller to the HHI register area .../bindings/clock/amlogic,meson8b-clkc.txt | 13 ++++------ arch/arm/boot/dts/meson.dtsi | 7 ++++++ arch/arm/boot/dts/meson8.dtsi | 15 ++++++------ arch/arm/boot/dts/meson8b.dtsi | 15 ++++++------ drivers/clk/meson/meson8b.c | 24 ++++++++++++------- 5 files changed, 43 insertions(+), 31 deletions(-)