| Message ID | 20190115123315.11069-1-narmstrong@baylibre.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | drm/meson: Add support for HDMI2.0 4k60 | expand |
Hi Andrzej, Laurent, On 15/01/2019 13:33, Neil Armstrong wrote: > This patchset aims to add support for the following HDMI2.0 4k60 modes: > - 594Mhz TMDS frequency needing TMDS Scramling and 1/40 rate for RGB/YUV4:4:4 > - 297MHz TMDS frequency with YUV4:2:0 encoding > > The first mode uses the SCDC helpers introduced by intel to : > - discover where the monitor support SCDC > - setup the SCDC parameters > This is implemented in the dw-hdmi bridge driver by handling scrambling > support during the bridge setup and by exporting an helper for the PHY > setup to setup the SCDC configuration for the 1/40 TMDS rate. > This code will only be active if the encoder support a TMDS rate > 340MHz. > > This patch could eventually break support on different SoC when connected > on a 4k60 monitor with SCDC : > - i.MX correctly discards pixel clocks > 216MHz > - R-CAR discards discards pixel clocks > 297MHz since [1] > - Rockchip discards invalid pixel clocks not in the rockchip_mpll_cfg table > - sun8i correctly discards pixel clocks > 297MHz on a83t > - sun8i discards discards pixel clocks > 594Mhz on h6, which is already broken > > First patch should fix support for Allwinner H6. > > The second mode is implemented by added the missing 4:2:0 bypass handling > in the dw-hdmi bridge driver and adding a "mtmdsclock" separating the > pixel clock from the tmds clock in the mode setup phase. > We also enable support for these modes in the connector only if the platform > glue code explicits the support. Do you think patches 1-4 could be applied ? Then we could focus on how we manage the bus format between the encoder and the bridge ? Especially patch 5 linked to patch 7. Will one of you be at FOSDEM 2019 ? we could chat about this. Following subjects on the table will be : - HDR metadata transmission aligned with the last patchset sent by intel-gfx - Colorspace connector property aligned with the last patchset sent by intel-gfx - HDCP 1.4 and 2.2 handling Neil > > Only the meson DRM dw_hdmi glue allows ycbcr420 modes, so no breakage > is expected here. > > The remaining patches adds support for : > - 1/40 TMDS rate aka DIV40 in the dw-hdmi meson PHY setup > - 4:2:0 output and clock setup > > The dw-hdmi support re-uses the support done by Rockchip engineers on the > Linux 4.4 BSP kernel. > > These modes has been validated using a MuxLab HDMI Signal Analyser in > addition to different UHD TVs supporting full 4k60 or the 4:2:0 variant. > > Changes since RFC v2 at [3]: > - Collected tested-by and reviewed-by tags > - Changed if condition in "add HDMI div40 TMDS mode" > - Updated "Add YUV420 output support" with the same if condition > > Changes since RFC v1 at [2]: > - Fix all comments from Laurent : > - Add define for HDMI 1.4 max tmds clock and SCDC supported version > - Call dw_hdmi_set_high_tmds_clock_ratio() in dw_hdmi_phy_enable_powerdown() > to unbreak Allwinner H6 > - Pass in_t(u8, bytes, SCDC_MIN_SOURCE_VERSION) as SCDC version > - Finally add comments for SCDC and Scrambling process > > [1] https://patchwork.freedesktop.org/patch/263616/ > [2] https://patchwork.freedesktop.org/series/52950/#rev1 > [3] https://patchwork.freedesktop.org/series/52950/#rev2 > > Neil Armstrong (7): > drm/bridge: dw-hdmi: Add SCDC and TMDS Scrambling support > drm/meson: add HDMI div40 TMDS mode > drm/meson: add support for HDMI2.0 2160p modes > drm/bridge: dw-hdmi: add support for YUV420 output > drm/bridge: dw-hdmi: allow ycbcr420 modes for >= 0x200a > drm/meson: Add YUV420 output support > drm/meson: Output in YUV444 if sink supports it > > Zheng Yang (1): > drm/bridge: dw-hdmi: support dynamically get input/out color info > > drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 182 +++++++++++++++++++--- > drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 1 + > drivers/gpu/drm/meson/meson_dw_hdmi.c | 128 ++++++++++++--- > drivers/gpu/drm/meson/meson_vclk.c | 93 ++++++++--- > drivers/gpu/drm/meson/meson_vclk.h | 7 +- > drivers/gpu/drm/meson/meson_venc.c | 8 +- > drivers/gpu/drm/meson/meson_venc.h | 11 ++ > drivers/gpu/drm/meson/meson_venc_cvbs.c | 3 +- > include/drm/bridge/dw_hdmi.h | 7 + > 9 files changed, 374 insertions(+), 66 deletions(-) >
On 31.01.2019 14:25, Neil Armstrong wrote: > Hi Andrzej, Laurent, > > On 15/01/2019 13:33, Neil Armstrong wrote: >> This patchset aims to add support for the following HDMI2.0 4k60 modes: >> - 594Mhz TMDS frequency needing TMDS Scramling and 1/40 rate for RGB/YUV4:4:4 >> - 297MHz TMDS frequency with YUV4:2:0 encoding >> >> The first mode uses the SCDC helpers introduced by intel to : >> - discover where the monitor support SCDC >> - setup the SCDC parameters >> This is implemented in the dw-hdmi bridge driver by handling scrambling >> support during the bridge setup and by exporting an helper for the PHY >> setup to setup the SCDC configuration for the 1/40 TMDS rate. >> This code will only be active if the encoder support a TMDS rate > 340MHz. >> >> This patch could eventually break support on different SoC when connected >> on a 4k60 monitor with SCDC : >> - i.MX correctly discards pixel clocks > 216MHz >> - R-CAR discards discards pixel clocks > 297MHz since [1] >> - Rockchip discards invalid pixel clocks not in the rockchip_mpll_cfg table >> - sun8i correctly discards pixel clocks > 297MHz on a83t >> - sun8i discards discards pixel clocks > 594Mhz on h6, which is already broken >> >> First patch should fix support for Allwinner H6. >> >> The second mode is implemented by added the missing 4:2:0 bypass handling >> in the dw-hdmi bridge driver and adding a "mtmdsclock" separating the >> pixel clock from the tmds clock in the mode setup phase. >> We also enable support for these modes in the connector only if the platform >> glue code explicits the support. > Do you think patches 1-4 could be applied ? For me they are OK. Should I take them via drm-misc? > > Then we could focus on how we manage the bus format between the encoder > and the bridge ? > > Especially patch 5 linked to patch 7. > > Will one of you be at FOSDEM 2019 ? we could chat about this. Nope. Regards Andrzej > > Following subjects on the table will be : > - HDR metadata transmission aligned with the last patchset sent by intel-gfx > - Colorspace connector property aligned with the last patchset sent by intel-gfx > - HDCP 1.4 and 2.2 handling > > Neil > >> Only the meson DRM dw_hdmi glue allows ycbcr420 modes, so no breakage >> is expected here. >> >> The remaining patches adds support for : >> - 1/40 TMDS rate aka DIV40 in the dw-hdmi meson PHY setup >> - 4:2:0 output and clock setup >> >> The dw-hdmi support re-uses the support done by Rockchip engineers on the >> Linux 4.4 BSP kernel. >> >> These modes has been validated using a MuxLab HDMI Signal Analyser in >> addition to different UHD TVs supporting full 4k60 or the 4:2:0 variant. >> >> Changes since RFC v2 at [3]: >> - Collected tested-by and reviewed-by tags >> - Changed if condition in "add HDMI div40 TMDS mode" >> - Updated "Add YUV420 output support" with the same if condition >> >> Changes since RFC v1 at [2]: >> - Fix all comments from Laurent : >> - Add define for HDMI 1.4 max tmds clock and SCDC supported version >> - Call dw_hdmi_set_high_tmds_clock_ratio() in dw_hdmi_phy_enable_powerdown() >> to unbreak Allwinner H6 >> - Pass in_t(u8, bytes, SCDC_MIN_SOURCE_VERSION) as SCDC version >> - Finally add comments for SCDC and Scrambling process >> >> [1] https://patchwork.freedesktop.org/patch/263616/ >> [2] https://patchwork.freedesktop.org/series/52950/#rev1 >> [3] https://patchwork.freedesktop.org/series/52950/#rev2 >> >> Neil Armstrong (7): >> drm/bridge: dw-hdmi: Add SCDC and TMDS Scrambling support >> drm/meson: add HDMI div40 TMDS mode >> drm/meson: add support for HDMI2.0 2160p modes >> drm/bridge: dw-hdmi: add support for YUV420 output >> drm/bridge: dw-hdmi: allow ycbcr420 modes for >= 0x200a >> drm/meson: Add YUV420 output support >> drm/meson: Output in YUV444 if sink supports it >> >> Zheng Yang (1): >> drm/bridge: dw-hdmi: support dynamically get input/out color info >> >> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 182 +++++++++++++++++++--- >> drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 1 + >> drivers/gpu/drm/meson/meson_dw_hdmi.c | 128 ++++++++++++--- >> drivers/gpu/drm/meson/meson_vclk.c | 93 ++++++++--- >> drivers/gpu/drm/meson/meson_vclk.h | 7 +- >> drivers/gpu/drm/meson/meson_venc.c | 8 +- >> drivers/gpu/drm/meson/meson_venc.h | 11 ++ >> drivers/gpu/drm/meson/meson_venc_cvbs.c | 3 +- >> include/drm/bridge/dw_hdmi.h | 7 + >> 9 files changed, 374 insertions(+), 66 deletions(-) >> > >
On 31/01/2019 15:13, Andrzej Hajda wrote: > On 31.01.2019 14:25, Neil Armstrong wrote: >> Hi Andrzej, Laurent, >> >> On 15/01/2019 13:33, Neil Armstrong wrote: >>> This patchset aims to add support for the following HDMI2.0 4k60 modes: >>> - 594Mhz TMDS frequency needing TMDS Scramling and 1/40 rate for RGB/YUV4:4:4 >>> - 297MHz TMDS frequency with YUV4:2:0 encoding >>> >>> The first mode uses the SCDC helpers introduced by intel to : >>> - discover where the monitor support SCDC >>> - setup the SCDC parameters >>> This is implemented in the dw-hdmi bridge driver by handling scrambling >>> support during the bridge setup and by exporting an helper for the PHY >>> setup to setup the SCDC configuration for the 1/40 TMDS rate. >>> This code will only be active if the encoder support a TMDS rate > 340MHz. >>> >>> This patch could eventually break support on different SoC when connected >>> on a 4k60 monitor with SCDC : >>> - i.MX correctly discards pixel clocks > 216MHz >>> - R-CAR discards discards pixel clocks > 297MHz since [1] >>> - Rockchip discards invalid pixel clocks not in the rockchip_mpll_cfg table >>> - sun8i correctly discards pixel clocks > 297MHz on a83t >>> - sun8i discards discards pixel clocks > 594Mhz on h6, which is already broken >>> >>> First patch should fix support for Allwinner H6. >>> >>> The second mode is implemented by added the missing 4:2:0 bypass handling >>> in the dw-hdmi bridge driver and adding a "mtmdsclock" separating the >>> pixel clock from the tmds clock in the mode setup phase. >>> We also enable support for these modes in the connector only if the platform >>> glue code explicits the support. >> Do you think patches 1-4 could be applied ? > > > For me they are OK. > > Should I take them via drm-misc? OK for me ! Neil > > >> >> Then we could focus on how we manage the bus format between the encoder >> and the bridge ? >> >> Especially patch 5 linked to patch 7. >> >> Will one of you be at FOSDEM 2019 ? we could chat about this. > > > Nope. > > > Regards > > Andrzej > > >> >> Following subjects on the table will be : >> - HDR metadata transmission aligned with the last patchset sent by intel-gfx >> - Colorspace connector property aligned with the last patchset sent by intel-gfx >> - HDCP 1.4 and 2.2 handling >> >> Neil >> >>> Only the meson DRM dw_hdmi glue allows ycbcr420 modes, so no breakage >>> is expected here. >>> >>> The remaining patches adds support for : >>> - 1/40 TMDS rate aka DIV40 in the dw-hdmi meson PHY setup >>> - 4:2:0 output and clock setup >>> >>> The dw-hdmi support re-uses the support done by Rockchip engineers on the >>> Linux 4.4 BSP kernel. >>> >>> These modes has been validated using a MuxLab HDMI Signal Analyser in >>> addition to different UHD TVs supporting full 4k60 or the 4:2:0 variant. >>> >>> Changes since RFC v2 at [3]: >>> - Collected tested-by and reviewed-by tags >>> - Changed if condition in "add HDMI div40 TMDS mode" >>> - Updated "Add YUV420 output support" with the same if condition >>> >>> Changes since RFC v1 at [2]: >>> - Fix all comments from Laurent : >>> - Add define for HDMI 1.4 max tmds clock and SCDC supported version >>> - Call dw_hdmi_set_high_tmds_clock_ratio() in dw_hdmi_phy_enable_powerdown() >>> to unbreak Allwinner H6 >>> - Pass in_t(u8, bytes, SCDC_MIN_SOURCE_VERSION) as SCDC version >>> - Finally add comments for SCDC and Scrambling process >>> >>> [1] https://patchwork.freedesktop.org/patch/263616/ >>> [2] https://patchwork.freedesktop.org/series/52950/#rev1 >>> [3] https://patchwork.freedesktop.org/series/52950/#rev2 >>> >>> Neil Armstrong (7): >>> drm/bridge: dw-hdmi: Add SCDC and TMDS Scrambling support >>> drm/meson: add HDMI div40 TMDS mode >>> drm/meson: add support for HDMI2.0 2160p modes >>> drm/bridge: dw-hdmi: add support for YUV420 output >>> drm/bridge: dw-hdmi: allow ycbcr420 modes for >= 0x200a >>> drm/meson: Add YUV420 output support >>> drm/meson: Output in YUV444 if sink supports it >>> >>> Zheng Yang (1): >>> drm/bridge: dw-hdmi: support dynamically get input/out color info >>> >>> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 182 +++++++++++++++++++--- >>> drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 1 + >>> drivers/gpu/drm/meson/meson_dw_hdmi.c | 128 ++++++++++++--- >>> drivers/gpu/drm/meson/meson_vclk.c | 93 ++++++++--- >>> drivers/gpu/drm/meson/meson_vclk.h | 7 +- >>> drivers/gpu/drm/meson/meson_venc.c | 8 +- >>> drivers/gpu/drm/meson/meson_venc.h | 11 ++ >>> drivers/gpu/drm/meson/meson_venc_cvbs.c | 3 +- >>> include/drm/bridge/dw_hdmi.h | 7 + >>> 9 files changed, 374 insertions(+), 66 deletions(-) >>> >> >> > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel >
Hi Neil, On Thu, Jan 31, 2019 at 02:25:30PM +0100, Neil Armstrong wrote: > On 15/01/2019 13:33, Neil Armstrong wrote: > > This patchset aims to add support for the following HDMI2.0 4k60 modes: > > - 594Mhz TMDS frequency needing TMDS Scramling and 1/40 rate for RGB/YUV4:4:4 > > - 297MHz TMDS frequency with YUV4:2:0 encoding > > > > The first mode uses the SCDC helpers introduced by intel to : > > - discover where the monitor support SCDC > > - setup the SCDC parameters > > This is implemented in the dw-hdmi bridge driver by handling scrambling > > support during the bridge setup and by exporting an helper for the PHY > > setup to setup the SCDC configuration for the 1/40 TMDS rate. > > This code will only be active if the encoder support a TMDS rate > 340MHz. > > > > This patch could eventually break support on different SoC when connected > > on a 4k60 monitor with SCDC : > > - i.MX correctly discards pixel clocks > 216MHz > > - R-CAR discards discards pixel clocks > 297MHz since [1] > > - Rockchip discards invalid pixel clocks not in the rockchip_mpll_cfg table > > - sun8i correctly discards pixel clocks > 297MHz on a83t > > - sun8i discards discards pixel clocks > 594Mhz on h6, which is already broken > > > > First patch should fix support for Allwinner H6. > > > > The second mode is implemented by added the missing 4:2:0 bypass handling > > in the dw-hdmi bridge driver and adding a "mtmdsclock" separating the > > pixel clock from the tmds clock in the mode setup phase. > > We also enable support for these modes in the connector only if the platform > > glue code explicits the support. > > Do you think patches 1-4 could be applied ? I would have liked it if there could be a way to avoid exporting dw_hdmi_set_high_tmds_clock_ratio() in patch 1/8, but if that's not possible, so be it (I haven't researched that myself). No issue with patches 2/8 to 4/8. > Then we could focus on how we manage the bus format between the encoder > and the bridge ? > > Especially patch 5 linked to patch 7. > > Will one of you be at FOSDEM 2019 ? we could chat about this. I will be there on Sunday, likely from around 11:00. > Following subjects on the table will be : > - HDR metadata transmission aligned with the last patchset sent by intel-gfx > - Colorspace connector property aligned with the last patchset sent by intel-gfx > - HDCP 1.4 and 2.2 handling > > > Only the meson DRM dw_hdmi glue allows ycbcr420 modes, so no breakage > > is expected here. > > > > The remaining patches adds support for : > > - 1/40 TMDS rate aka DIV40 in the dw-hdmi meson PHY setup > > - 4:2:0 output and clock setup > > > > The dw-hdmi support re-uses the support done by Rockchip engineers on the > > Linux 4.4 BSP kernel. > > > > These modes has been validated using a MuxLab HDMI Signal Analyser in > > addition to different UHD TVs supporting full 4k60 or the 4:2:0 variant. > > > > Changes since RFC v2 at [3]: > > - Collected tested-by and reviewed-by tags > > - Changed if condition in "add HDMI div40 TMDS mode" > > - Updated "Add YUV420 output support" with the same if condition > > > > Changes since RFC v1 at [2]: > > - Fix all comments from Laurent : > > - Add define for HDMI 1.4 max tmds clock and SCDC supported version > > - Call dw_hdmi_set_high_tmds_clock_ratio() in dw_hdmi_phy_enable_powerdown() > > to unbreak Allwinner H6 > > - Pass in_t(u8, bytes, SCDC_MIN_SOURCE_VERSION) as SCDC version > > - Finally add comments for SCDC and Scrambling process > > > > [1] https://patchwork.freedesktop.org/patch/263616/ > > [2] https://patchwork.freedesktop.org/series/52950/#rev1 > > [3] https://patchwork.freedesktop.org/series/52950/#rev2 > > > > Neil Armstrong (7): > > drm/bridge: dw-hdmi: Add SCDC and TMDS Scrambling support > > drm/meson: add HDMI div40 TMDS mode > > drm/meson: add support for HDMI2.0 2160p modes > > drm/bridge: dw-hdmi: add support for YUV420 output > > drm/bridge: dw-hdmi: allow ycbcr420 modes for >= 0x200a > > drm/meson: Add YUV420 output support > > drm/meson: Output in YUV444 if sink supports it > > > > Zheng Yang (1): > > drm/bridge: dw-hdmi: support dynamically get input/out color info > > > > drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 182 +++++++++++++++++++--- > > drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 1 + > > drivers/gpu/drm/meson/meson_dw_hdmi.c | 128 ++++++++++++--- > > drivers/gpu/drm/meson/meson_vclk.c | 93 ++++++++--- > > drivers/gpu/drm/meson/meson_vclk.h | 7 +- > > drivers/gpu/drm/meson/meson_venc.c | 8 +- > > drivers/gpu/drm/meson/meson_venc.h | 11 ++ > > drivers/gpu/drm/meson/meson_venc_cvbs.c | 3 +- > > include/drm/bridge/dw_hdmi.h | 7 + > > 9 files changed, 374 insertions(+), 66 deletions(-)
On 31.01.2019 16:50, Neil Armstrong wrote: > On 31/01/2019 15:13, Andrzej Hajda wrote: >> On 31.01.2019 14:25, Neil Armstrong wrote: >>> Hi Andrzej, Laurent, >>> >>> On 15/01/2019 13:33, Neil Armstrong wrote: >>>> This patchset aims to add support for the following HDMI2.0 4k60 modes: >>>> - 594Mhz TMDS frequency needing TMDS Scramling and 1/40 rate for RGB/YUV4:4:4 >>>> - 297MHz TMDS frequency with YUV4:2:0 encoding >>>> >>>> The first mode uses the SCDC helpers introduced by intel to : >>>> - discover where the monitor support SCDC >>>> - setup the SCDC parameters >>>> This is implemented in the dw-hdmi bridge driver by handling scrambling >>>> support during the bridge setup and by exporting an helper for the PHY >>>> setup to setup the SCDC configuration for the 1/40 TMDS rate. >>>> This code will only be active if the encoder support a TMDS rate > 340MHz. >>>> >>>> This patch could eventually break support on different SoC when connected >>>> on a 4k60 monitor with SCDC : >>>> - i.MX correctly discards pixel clocks > 216MHz >>>> - R-CAR discards discards pixel clocks > 297MHz since [1] >>>> - Rockchip discards invalid pixel clocks not in the rockchip_mpll_cfg table >>>> - sun8i correctly discards pixel clocks > 297MHz on a83t >>>> - sun8i discards discards pixel clocks > 594Mhz on h6, which is already broken >>>> >>>> First patch should fix support for Allwinner H6. >>>> >>>> The second mode is implemented by added the missing 4:2:0 bypass handling >>>> in the dw-hdmi bridge driver and adding a "mtmdsclock" separating the >>>> pixel clock from the tmds clock in the mode setup phase. >>>> We also enable support for these modes in the connector only if the platform >>>> glue code explicits the support. >>> Do you think patches 1-4 could be applied ? >> >> For me they are OK. >> >> Should I take them via drm-misc? > OK for me ! > > Neil These patches do not apply. Could you rebase them on drm-misc-next. Regards Andrzej > >> >>> Then we could focus on how we manage the bus format between the encoder >>> and the bridge ? >>> >>> Especially patch 5 linked to patch 7. >>> >>> Will one of you be at FOSDEM 2019 ? we could chat about this. >> >> Nope. >> >> >> Regards >> >> Andrzej >> >> >>> Following subjects on the table will be : >>> - HDR metadata transmission aligned with the last patchset sent by intel-gfx >>> - Colorspace connector property aligned with the last patchset sent by intel-gfx >>> - HDCP 1.4 and 2.2 handling >>> >>> Neil >>> >>>> Only the meson DRM dw_hdmi glue allows ycbcr420 modes, so no breakage >>>> is expected here. >>>> >>>> The remaining patches adds support for : >>>> - 1/40 TMDS rate aka DIV40 in the dw-hdmi meson PHY setup >>>> - 4:2:0 output and clock setup >>>> >>>> The dw-hdmi support re-uses the support done by Rockchip engineers on the >>>> Linux 4.4 BSP kernel. >>>> >>>> These modes has been validated using a MuxLab HDMI Signal Analyser in >>>> addition to different UHD TVs supporting full 4k60 or the 4:2:0 variant. >>>> >>>> Changes since RFC v2 at [3]: >>>> - Collected tested-by and reviewed-by tags >>>> - Changed if condition in "add HDMI div40 TMDS mode" >>>> - Updated "Add YUV420 output support" with the same if condition >>>> >>>> Changes since RFC v1 at [2]: >>>> - Fix all comments from Laurent : >>>> - Add define for HDMI 1.4 max tmds clock and SCDC supported version >>>> - Call dw_hdmi_set_high_tmds_clock_ratio() in dw_hdmi_phy_enable_powerdown() >>>> to unbreak Allwinner H6 >>>> - Pass in_t(u8, bytes, SCDC_MIN_SOURCE_VERSION) as SCDC version >>>> - Finally add comments for SCDC and Scrambling process >>>> >>>> [1] https://patchwork.freedesktop.org/patch/263616/ >>>> [2] https://patchwork.freedesktop.org/series/52950/#rev1 >>>> [3] https://patchwork.freedesktop.org/series/52950/#rev2 >>>> >>>> Neil Armstrong (7): >>>> drm/bridge: dw-hdmi: Add SCDC and TMDS Scrambling support >>>> drm/meson: add HDMI div40 TMDS mode >>>> drm/meson: add support for HDMI2.0 2160p modes >>>> drm/bridge: dw-hdmi: add support for YUV420 output >>>> drm/bridge: dw-hdmi: allow ycbcr420 modes for >= 0x200a >>>> drm/meson: Add YUV420 output support >>>> drm/meson: Output in YUV444 if sink supports it >>>> >>>> Zheng Yang (1): >>>> drm/bridge: dw-hdmi: support dynamically get input/out color info >>>> >>>> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 182 +++++++++++++++++++--- >>>> drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 1 + >>>> drivers/gpu/drm/meson/meson_dw_hdmi.c | 128 ++++++++++++--- >>>> drivers/gpu/drm/meson/meson_vclk.c | 93 ++++++++--- >>>> drivers/gpu/drm/meson/meson_vclk.h | 7 +- >>>> drivers/gpu/drm/meson/meson_venc.c | 8 +- >>>> drivers/gpu/drm/meson/meson_venc.h | 11 ++ >>>> drivers/gpu/drm/meson/meson_venc_cvbs.c | 3 +- >>>> include/drm/bridge/dw_hdmi.h | 7 + >>>> 9 files changed, 374 insertions(+), 66 deletions(-) >>>> >>> >> _______________________________________________ >> dri-devel mailing list >> dri-devel@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/dri-devel >> > >
Le 01/02/2019 11:25, Andrzej Hajda a écrit : > On 31.01.2019 16:50, Neil Armstrong wrote: >> On 31/01/2019 15:13, Andrzej Hajda wrote: >>> On 31.01.2019 14:25, Neil Armstrong wrote: >>>> Hi Andrzej, Laurent, >>>> >>>> On 15/01/2019 13:33, Neil Armstrong wrote: >>>>> This patchset aims to add support for the following HDMI2.0 4k60 modes: >>>>> - 594Mhz TMDS frequency needing TMDS Scramling and 1/40 rate for RGB/YUV4:4:4 >>>>> - 297MHz TMDS frequency with YUV4:2:0 encoding >>>>> >>>>> The first mode uses the SCDC helpers introduced by intel to : >>>>> - discover where the monitor support SCDC >>>>> - setup the SCDC parameters >>>>> This is implemented in the dw-hdmi bridge driver by handling scrambling >>>>> support during the bridge setup and by exporting an helper for the PHY >>>>> setup to setup the SCDC configuration for the 1/40 TMDS rate. >>>>> This code will only be active if the encoder support a TMDS rate > 340MHz. >>>>> >>>>> This patch could eventually break support on different SoC when connected >>>>> on a 4k60 monitor with SCDC : >>>>> - i.MX correctly discards pixel clocks > 216MHz >>>>> - R-CAR discards discards pixel clocks > 297MHz since [1] >>>>> - Rockchip discards invalid pixel clocks not in the rockchip_mpll_cfg table >>>>> - sun8i correctly discards pixel clocks > 297MHz on a83t >>>>> - sun8i discards discards pixel clocks > 594Mhz on h6, which is already broken >>>>> >>>>> First patch should fix support for Allwinner H6. >>>>> >>>>> The second mode is implemented by added the missing 4:2:0 bypass handling >>>>> in the dw-hdmi bridge driver and adding a "mtmdsclock" separating the >>>>> pixel clock from the tmds clock in the mode setup phase. >>>>> We also enable support for these modes in the connector only if the platform >>>>> glue code explicits the support. >>>> Do you think patches 1-4 could be applied ? >>> >>> For me they are OK. >>> >>> Should I take them via drm-misc? >> OK for me ! >> >> Neil > > > These patches do not apply. Could you rebase them on drm-misc-next. Sure, re-spinning. Neil > > > Regards > > Andrzej > > > >> >>> >>>> Then we could focus on how we manage the bus format between the encoder >>>> and the bridge ? >>>> >>>> Especially patch 5 linked to patch 7. >>>> >>>> Will one of you be at FOSDEM 2019 ? we could chat about this. >>> >>> Nope. >>> >>> >>> Regards >>> >>> Andrzej >>> >>> >>>> Following subjects on the table will be : >>>> - HDR metadata transmission aligned with the last patchset sent by intel-gfx >>>> - Colorspace connector property aligned with the last patchset sent by intel-gfx >>>> - HDCP 1.4 and 2.2 handling >>>> >>>> Neil >>>> >>>>> Only the meson DRM dw_hdmi glue allows ycbcr420 modes, so no breakage >>>>> is expected here. >>>>> >>>>> The remaining patches adds support for : >>>>> - 1/40 TMDS rate aka DIV40 in the dw-hdmi meson PHY setup >>>>> - 4:2:0 output and clock setup >>>>> >>>>> The dw-hdmi support re-uses the support done by Rockchip engineers on the >>>>> Linux 4.4 BSP kernel. >>>>> >>>>> These modes has been validated using a MuxLab HDMI Signal Analyser in >>>>> addition to different UHD TVs supporting full 4k60 or the 4:2:0 variant. >>>>> >>>>> Changes since RFC v2 at [3]: >>>>> - Collected tested-by and reviewed-by tags >>>>> - Changed if condition in "add HDMI div40 TMDS mode" >>>>> - Updated "Add YUV420 output support" with the same if condition >>>>> >>>>> Changes since RFC v1 at [2]: >>>>> - Fix all comments from Laurent : >>>>> - Add define for HDMI 1.4 max tmds clock and SCDC supported version >>>>> - Call dw_hdmi_set_high_tmds_clock_ratio() in dw_hdmi_phy_enable_powerdown() >>>>> to unbreak Allwinner H6 >>>>> - Pass in_t(u8, bytes, SCDC_MIN_SOURCE_VERSION) as SCDC version >>>>> - Finally add comments for SCDC and Scrambling process >>>>> >>>>> [1] https://patchwork.freedesktop.org/patch/263616/ >>>>> [2] https://patchwork.freedesktop.org/series/52950/#rev1 >>>>> [3] https://patchwork.freedesktop.org/series/52950/#rev2 >>>>> >>>>> Neil Armstrong (7): >>>>> drm/bridge: dw-hdmi: Add SCDC and TMDS Scrambling support >>>>> drm/meson: add HDMI div40 TMDS mode >>>>> drm/meson: add support for HDMI2.0 2160p modes >>>>> drm/bridge: dw-hdmi: add support for YUV420 output >>>>> drm/bridge: dw-hdmi: allow ycbcr420 modes for >= 0x200a >>>>> drm/meson: Add YUV420 output support >>>>> drm/meson: Output in YUV444 if sink supports it >>>>> >>>>> Zheng Yang (1): >>>>> drm/bridge: dw-hdmi: support dynamically get input/out color info >>>>> >>>>> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 182 +++++++++++++++++++--- >>>>> drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 1 + >>>>> drivers/gpu/drm/meson/meson_dw_hdmi.c | 128 ++++++++++++--- >>>>> drivers/gpu/drm/meson/meson_vclk.c | 93 ++++++++--- >>>>> drivers/gpu/drm/meson/meson_vclk.h | 7 +- >>>>> drivers/gpu/drm/meson/meson_venc.c | 8 +- >>>>> drivers/gpu/drm/meson/meson_venc.h | 11 ++ >>>>> drivers/gpu/drm/meson/meson_venc_cvbs.c | 3 +- >>>>> include/drm/bridge/dw_hdmi.h | 7 + >>>>> 9 files changed, 374 insertions(+), 66 deletions(-) >>>>> >>>> >>> _______________________________________________ >>> dri-devel mailing list >>> dri-devel@lists.freedesktop.org >>> https://lists.freedesktop.org/mailman/listinfo/dri-devel >>> >> >> >