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[176.150.251.154]) by smtp.gmail.com with ESMTPSA id d17sm25806547wrm.52.2019.08.22.07.24.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2019 07:24:58 -0700 (PDT) From: Neil Armstrong To: khilman@baylibre.com, jbrunet@baylibre.com Subject: [PATCH 0/6] arm64: meson-sm1: add support for DVFS Date: Thu, 22 Aug 2019 16:24:49 +0200 Message-Id: <20190822142455.12506-1-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190822_072500_587261_FDDAD189 X-CRM114-Status: UNSURE ( 9.11 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:443 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Neil Armstrong Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org Following DVFS support for the Amlogic G12A and G12B SoCs, this serie enables DVFS on the SM1 SoC for the SEI610 board. The SM1 Clock structure is slightly different because of the Cortex-A55 core used, having the capability for each core of a same cluster to run at a different frequency thanks to the newly used DynamIQ Shared Unit. This is why SM1 has a CPU clock tree for each core and for DynamIQ Shared Unit, with a bypass mux to use the CPU0 instead of the dedicated trees. The DSU uses a new GP1 PLL as default clock, thus GP1 is added as read-only. The SM1 OPPs has been taken from the Amlogic Vendor tree, and unlike G12A only a single version of the SoC is available. Dependencies: - patch 6 is based on the "arm64: meson: add support for SM1 Power Domains" serie, but is not a strong dependency, it will work without Neil Armstrong (6): dt-bindings: clk: meson: add sm1 periph clock controller bindings clk: meson: g12a: add support for SM1 GP1 PLL clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks clk: meson: g12a: expose SM1 CPU 1, 2 & 3 clocks arm64: dts: meson-sm1-sei610: enable DVFS .../bindings/clock/amlogic,gxbb-clkc.txt | 1 + .../boot/dts/amlogic/meson-sm1-sei610.dts | 59 +- arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 69 +++ drivers/clk/meson/g12a.c | 544 ++++++++++++++++++ drivers/clk/meson/g12a.h | 26 +- include/dt-bindings/clock/g12a-clkc.h | 3 + 6 files changed, 697 insertions(+), 5 deletions(-)