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Mon, 07 Sep 2020 01:18:29 -0700 (PDT) From: Neil Armstrong To: daniel@ffwll.ch Subject: [PATCH 0/6] drm/meson: add support for AXG & MIPI-DSI Date: Mon, 7 Sep 2020 10:18:19 +0200 Message-Id: <20200907081825.1654-1-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200907_041831_520947_A2BACC6C X-CRM114-Status: GOOD ( 12.74 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2a00:1450:4864:20:0:0:0:341 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Neil Armstrong Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org The Amlogic AXG SoC family has a downgraded VPU with the following changes : - Only a single OSD plane, no overlay video plane - The primary plane doesn't support HW scaling - The pixels are read directly from DDR without any Canvas module - Doesn't support HDMI or CVBS - Ouputs only with ENCL encoder to a DPI-to-DSI Synopsys DW-MIPI-DSI transceiver The Amlogic AXg SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom glue managing the IP resets, clock and data input similar to the DW-HDMI Glue on other Amlogic SoCs. This adds support for the Glue managing the transceiver, mimicing the init flow provided by Amlogic to setup the ENCl encoder, the glue, the transceiver, the digital D-PHY and the Analog PHY in the proper way. The DW-MIPI-DSI transceiver + D-PHY are directly clocked by the VCLK2 clock, which pixel clock is derived and feeds the ENCL encoder and the VIU pixel reader. An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the DW-MIPI-DSI transceiver. Neil Armstrong (6): dt-bindings: display: amlogic,meson-vpu: add bindings for VPU found in AXG SoCs dt-bindings: display: add Amlogic MIPI DSI Host Controller bindings drm/meson: add support for VPU found in AXG SoCs drm/meson: venc: add ENCL encoder setup for MIPI-DSI output drm/meson: remove useless recursive components matching drm/meson: add support for MIPI-DSI transceiver .../display/amlogic,meson-dw-mipi-dsi.yaml | 115 ++++ .../bindings/display/amlogic,meson-vpu.yaml | 36 +- drivers/gpu/drm/meson/Kconfig | 7 + drivers/gpu/drm/meson/Makefile | 1 + drivers/gpu/drm/meson/meson_crtc.c | 8 +- drivers/gpu/drm/meson/meson_drv.c | 163 ++--- drivers/gpu/drm/meson/meson_drv.h | 10 +- drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 562 ++++++++++++++++++ drivers/gpu/drm/meson/meson_plane.c | 74 ++- drivers/gpu/drm/meson/meson_registers.h | 1 + drivers/gpu/drm/meson/meson_venc.c | 230 ++++++- drivers/gpu/drm/meson/meson_venc.h | 6 + drivers/gpu/drm/meson/meson_viu.c | 50 +- drivers/gpu/drm/meson/meson_vpp.c | 6 +- drivers/gpu/drm/meson/meson_vpp.h | 2 + 15 files changed, 1176 insertions(+), 95 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.c