[0/2] pwm: meson: make full use of common clock framework

Message

Heiner Kallweit April 8, 2023, 8:40 p.m. UTC

Newer versions of the PWM block use a core clock with external mux,
divider, and gate. These components either don't exist any longer in
the PWM block, or they are bypassed.
To minimize needed changes for supporting the new version, the internal
divider and gate should be handled by CCF too.

I didn't see a good way to split the patch, therefore it's somewhat
bigger. What it does:

- The internal mux is handled by CCF already. Register also internal
  divider and gate with CCF, so that we have one representation of the
  input clock: [mux] parent of [divider] parent of [gate]
  
- Now that CCF selects an appropriate mux parent, we don't need the
  DT-provided default parent any longer. Accordingly we can also omit
  setting the mux parent directly in the driver.
  
- Instead of manually handling the pre-div divider value, let CCF
  set the input clock. Targeted input clock frequency is
  0xffff * 1/period for best precision.
  
- For the "inverted pwm disabled" scenario target an input clock
  frequency of 1GHz. This ensures that the remaining low pulses
  have minimum length.

I don't have hw with the old PWM block, therefore I couldn't test this
patch. With the not yet included extension for the new PWM block
(channel->clock directly coming from get_clk(external_clk)) I didn't
notice any problem. My system uses PWM for the CPU voltage regulator
and for the SDIO 32kHz clock.

Note: The clock gate in the old PWM block is permanently disabled.
This seems to indicate that it's not used by the new PWM block.

Changes to RFT/RFC version:
- use parent_hws instead of parent_names for div/gate clock
- use devm_clk_hw_register where the struct clk * returned by
  devm_clk_register isn't needed

Heiner Kallweit (2):
  pwm: meson: make full use of common clock framework
  pwm: meson: omit video/hdmi clock as mux parent

 drivers/pwm/pwm-meson.c | 159 ++++++++++++++++++++--------------------
 1 file changed, 81 insertions(+), 78 deletions(-)

Comments

Martin Blumenstingl April 10, 2023, 10:15 p.m. UTC | #1

Hi Heiner,

On Sat, Apr 8, 2023 at 10:40 PM Heiner Kallweit <[e-mail]> wrote:
[...]
> I don't have hw with the old PWM block, therefore I couldn't test this
> patch. With the not yet included extension for the new PWM block
> (channel->clock directly coming from get_clk(external_clk)) I didn't
> notice any problem. My system uses PWM for the CPU voltage regulator
> and for the SDIO 32kHz clock.
I do have some issues with my Odroid-C1 board (it doesn't detect the
eMMC anymore, while u-boot does).
This unfortunately means that I currently cannot test 32-bit SoC
support at the moment as I am running out of time for today.
I'll bisect this issue in the next few days and then continue with
testing. So sorry that this is taking longer than expected.


Best regards,
Martin