From patchwork Mon Dec 10 16:04:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianxin Pan X-Patchwork-Id: 10721501 X-Patchwork-Delegate: neil.armstrong@linaro.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4898291E for ; Mon, 10 Dec 2018 16:07:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3834A29B2C for ; Mon, 10 Dec 2018 16:07:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2C7D22AE25; Mon, 10 Dec 2018 16:07:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0FD5B2AE0D for ; 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Mon, 10 Dec 2018 16:07:00 +0000 Received: from mail-sh2.amlogic.com ([58.32.228.45]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gWO4h-000240-LX; Mon, 10 Dec 2018 16:06:46 +0000 Received: from localhost.localdomain (10.18.11.217) by mail-sh2.amlogic.com (10.18.11.6) with Microsoft SMTP Server id 15.0.1320.4; Tue, 11 Dec 2018 00:05:19 +0800 From: Jianxin Pan To: Jerome Brunet , Neil Armstrong Subject: [PATCH RESEND v7 4/4] clk: meson: add one based divider support for sclk divider Date: Tue, 11 Dec 2018 00:04:36 +0800 Message-ID: <1544457877-51301-5-git-send-email-jianxin.pan@amlogic.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1544457877-51301-1-git-send-email-jianxin.pan@amlogic.com> References: <1544457877-51301-1-git-send-email-jianxin.pan@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.11.217] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181210_080628_158452_174047A5 X-CRM114-Status: GOOD ( 13.03 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Hanjie Lin , Victor Wan , Jianxin Pan , Stephen Boyd , Kevin Hilman , Michael Turquette , Yixun Lan , linux-kernel@vger.kernel.org, Boris Brezillon , Liang Yang , Jian Hu , Miquel Raynal , Carlo Caione , linux-amlogic@lists.infradead.org, Martin Blumenstingl , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Qiufang Dai Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP When CLK_DIVIDER_ONE_BASED flag is set, the sclk divider will be: one based divider (div = val), and zero value gates the clock Signed-off-by: Jianxin Pan --- drivers/clk/meson/clkc-audio.h | 1 + drivers/clk/meson/sclk-div.c | 28 ++++++++++++++++++---------- 2 files changed, 19 insertions(+), 10 deletions(-) diff --git a/drivers/clk/meson/clkc-audio.h b/drivers/clk/meson/clkc-audio.h index 0a7c157..9bd6ced 100644 --- a/drivers/clk/meson/clkc-audio.h +++ b/drivers/clk/meson/clkc-audio.h @@ -20,6 +20,7 @@ struct meson_sclk_div_data { struct parm hi; unsigned int cached_div; struct clk_duty cached_duty; + u8 flags; }; extern const struct clk_ops meson_clk_triphase_ops; diff --git a/drivers/clk/meson/sclk-div.c b/drivers/clk/meson/sclk-div.c index bc64019..d98707b 100644 --- a/drivers/clk/meson/sclk-div.c +++ b/drivers/clk/meson/sclk-div.c @@ -24,22 +24,23 @@ return (struct meson_sclk_div_data *)clk->data; } -static int sclk_div_maxval(struct meson_sclk_div_data *sclk) -{ - return (1 << sclk->div.width) - 1; -} - static int sclk_div_maxdiv(struct meson_sclk_div_data *sclk) { - return sclk_div_maxval(sclk) + 1; + if (sclk->flags & CLK_DIVIDER_ONE_BASED) + return clk_div_mask(sclk->div.width); + else + return clk_div_mask(sclk->div.width) + 1; } static int sclk_div_getdiv(struct clk_hw *hw, unsigned long rate, unsigned long prate, int maxdiv) { int div = DIV_ROUND_CLOSEST_ULL((u64)prate, rate); + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); + int mindiv = (sclk->flags & CLK_DIVIDER_ONE_BASED) ? 1 : 2; - return clamp(div, 2, maxdiv); + return clamp(div, mindiv, maxdiv); } static int sclk_div_bestdiv(struct clk_hw *hw, unsigned long rate, @@ -47,7 +48,7 @@ static int sclk_div_bestdiv(struct clk_hw *hw, unsigned long rate, struct meson_sclk_div_data *sclk) { struct clk_hw *parent = clk_hw_get_parent(hw); - int bestdiv = 0, i; + int bestdiv = 0, i, mindiv; unsigned long maxdiv, now, parent_now; unsigned long best = 0, best_parent = 0; @@ -64,8 +65,9 @@ static int sclk_div_bestdiv(struct clk_hw *hw, unsigned long rate, * unsigned long in rate * i below */ maxdiv = min(ULONG_MAX / rate, maxdiv); + mindiv = (sclk->flags & CLK_DIVIDER_ONE_BASED) ? 1 : 2; - for (i = 2; i <= maxdiv; i++) { + for (i = mindiv; i <= maxdiv; i++) { /* * It's the most ideal case if the requested rate can be * divided from parent clock without needing to change @@ -153,10 +155,14 @@ static int sclk_div_get_duty_cycle(struct clk_hw *hw, static void sclk_apply_divider(struct clk_regmap *clk, struct meson_sclk_div_data *sclk) { + unsigned int div; + if (MESON_PARM_APPLICABLE(&sclk->hi)) sclk_apply_ratio(clk, sclk); - meson_parm_write(clk->map, &sclk->div, sclk->cached_div - 1); + div = (sclk->flags & CLK_DIVIDER_ONE_BASED) ? + sclk->cached_div : (sclk->cached_div - 1); + meson_parm_write(clk->map, &sclk->div, div); } static int sclk_div_set_rate(struct clk_hw *hw, unsigned long rate, @@ -223,6 +229,8 @@ static void sclk_div_init(struct clk_hw *hw) /* if the divider is initially disabled, assume max */ if (!val) sclk->cached_div = sclk_div_maxdiv(sclk); + else if (sclk->flags & CLK_DIVIDER_ONE_BASED) + sclk->cached_div = val; else sclk->cached_div = val + 1;