From patchwork Mon Dec 17 16:24:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianxin Pan X-Patchwork-Id: 10733797 X-Patchwork-Delegate: neil.armstrong@linaro.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 03E3713BF for ; Mon, 17 Dec 2018 16:25:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E68DA2A1D2 for ; Mon, 17 Dec 2018 16:25:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D99B82A1D5; Mon, 17 Dec 2018 16:25:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7BC8E2A1D2 for ; Mon, 17 Dec 2018 16:25:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=bSu6AeNH6ch9jhQn1c8NEMN3WqM7sSU91PlpTmPCU78=; b=R2k1d1lHoSAhzX qhQ/qmTzpbo4aWrEXa3pUoTcQaXcUxiTN1ikGo5dpaXUNl33EUashVmxSyBNjxVJb27UQcYRdbt7Q SiInjtIAxEgXIVhjQfWgH6NZF+qbUI8Cfvk2bUUxpJFoQL1DNa6mi5GacGivQVl72Zz/LQmCjXK/X aGY3f+cHuj/ujFJ+WBegfmIDBxc+oRRpevrVl66nfdFyl3ieS9ameQ2nLL8BWZ9Z7aXLyZGBRY0J9 I8pB6dXbrDiXkVLdN88zM6vEEceESLnVXRawnTRkaUGkLklAMJJhoz8zuZ5haitf4t8EvZpWzv8uM RsmrAEPgjF3iF0CsHXIw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gYvi9-000567-TV; Mon, 17 Dec 2018 16:25:41 +0000 Received: from mail-sh2.amlogic.com ([58.32.228.45]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gYvhl-0003Xa-75; Mon, 17 Dec 2018 16:25:27 +0000 Received: from localhost.localdomain (10.18.11.217) by mail-sh2.amlogic.com (10.18.11.6) with Microsoft SMTP Server id 15.0.1320.4; Tue, 18 Dec 2018 00:24:49 +0800 From: Jianxin Pan To: Jerome Brunet , Neil Armstrong Subject: [PATCH v8 2/4] clk: meson: add emmc sub clock phase delay driver Date: Tue, 18 Dec 2018 00:24:08 +0800 Message-ID: <1545063850-21504-3-git-send-email-jianxin.pan@amlogic.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1545063850-21504-1-git-send-email-jianxin.pan@amlogic.com> References: <1545063850-21504-1-git-send-email-jianxin.pan@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.11.217] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181217_082517_725764_2881291F X-CRM114-Status: GOOD ( 12.57 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Hanjie Lin , Victor Wan , Jianxin Pan , Stephen Boyd , Kevin Hilman , Michael Turquette , Yixun Lan , linux-kernel@vger.kernel.org, Boris Brezillon , Liang Yang , Jian Hu , Miquel Raynal , Carlo Caione , linux-amlogic@lists.infradead.org, Martin Blumenstingl , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Qiufang Dai Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Yixun Lan Export the emmc sub clock phase delay ops which will be used by the emmc sub clock driver itself. Signed-off-by: Yixun Lan Signed-off-by: Jianxin Pan --- drivers/clk/meson/Makefile | 1 + drivers/clk/meson/clk-phase-delay.c | 70 +++++++++++++++++++++++++++++++++++++ drivers/clk/meson/clkc.h | 7 ++++ 3 files changed, 78 insertions(+) create mode 100644 drivers/clk/meson/clk-phase-delay.c diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index acd8694..d59620d 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -3,6 +3,7 @@ # obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o vid-pll-div.o +obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-phase-delay.o obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-input.o obj-$(CONFIG_COMMON_CLK_AMLOGIC) += sclk-div.o obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o diff --git a/drivers/clk/meson/clk-phase-delay.c b/drivers/clk/meson/clk-phase-delay.c new file mode 100644 index 0000000..88004d2 --- /dev/null +++ b/drivers/clk/meson/clk-phase-delay.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Amlogic Meson MMC Sub Clock Controller Driver + * + * Copyright (c) 2017 Baylibre SAS. + * Author: Jerome Brunet + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Yixun Lan + * Author: Jianxin Pan + */ + +#include +#include "clkc.h" + +static inline struct meson_clk_phase_delay_data * +meson_clk_get_phase_delay_data(struct clk_regmap *clk) +{ + return clk->data; +} + +static int meson_clk_phase_delay_get_phase(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_phase_delay_data *ph; + unsigned long period_ps, p, d; + int degrees; + + ph = meson_clk_get_phase_delay_data(clk); + p = meson_parm_read(clk->map, &ph->phase); + degrees = p * 360 / (1 << (ph->phase.width)); + + period_ps = DIV_ROUND_UP(NSEC_PER_SEC * 1000, + clk_hw_get_rate(hw)); + + d = meson_parm_read(clk->map, &ph->delay); + degrees += d * ph->delay_step_ps * 360 / period_ps; + degrees %= 360; + + return degrees; +} + +static int meson_clk_phase_delay_set_phase(struct clk_hw *hw, int degrees) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_phase_delay_data *ph; + unsigned long period_ps, d = 0, r; + + ph = meson_clk_get_phase_delay_data(clk); + period_ps = DIV_ROUND_UP(NSEC_PER_SEC * 1000, clk_hw_get_rate(hw)); + + /* + * First compute the phase index (p), the remainder (r) is the + * part we'll try to acheive using the delays (d). + */ + r = do_div(degrees, 360 / 1 << (ph->phase.width)); + d = DIV_ROUND_CLOSEST(r * period_ps, + 360 * ph->delay_step_ps); + d = min(d, PMASK(ph->delay.width)); + + meson_parm_write(clk->map, &ph->phase, degrees); + meson_parm_write(clk->map, &ph->delay, d); + return 0; +} + +const struct clk_ops meson_clk_phase_delay_ops = { + .get_phase = meson_clk_phase_delay_get_phase, + .set_phase = meson_clk_phase_delay_set_phase, +}; +EXPORT_SYMBOL_GPL(meson_clk_phase_delay_ops); diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index 00b3320..e6f0905 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -118,6 +118,12 @@ struct clk_regmap _name = { \ }, \ }; +struct meson_clk_phase_delay_data { + struct parm phase; + struct parm delay; + unsigned int delay_step_ps; +}; + /* clk_ops */ extern const struct clk_ops meson_clk_pll_ro_ops; extern const struct clk_ops meson_clk_pll_ops; @@ -127,6 +133,7 @@ struct clk_regmap _name = { \ extern const struct clk_ops meson_clk_phase_ops; extern const struct clk_ops meson_vid_pll_div_ro_ops; extern const struct clk_ops meson_sclk_div_ops; +extern const struct clk_ops meson_clk_phase_delay_ops; struct clk_hw *meson_clk_hw_register_input(struct device *dev, const char *of_name,