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[2003:dc:d3d2:e004:c1f3:de25:bb39:bc3b]) by smtp.googlemail.com with ESMTPSA id k56sm6909872wrk.45.2017.06.11.03.18.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 11 Jun 2017 03:18:16 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, jbrunet@baylibre.com, narmstrong@baylibre.com, khilman@baylibre.com, carlo@caione.org Subject: [PATCH 07/13] ARM: dts: meson8: add the pins for the SDIO controller Date: Sun, 11 Jun 2017 12:16:38 +0200 Message-Id: <20170611101644.28581-8-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.13.1 In-Reply-To: <20170611101644.28581-1-martin.blumenstingl@googlemail.com> References: <20170611101644.28581-1-martin.blumenstingl@googlemail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170611_031835_276391_06BBBC78 X-CRM114-Status: UNSURE ( 7.67 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Martin Blumenstingl , devicetree@vger.kernel.org, mturquette@baylibre.com, linux@armlinux.org.uk MIME-Version: 1.0 Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong --- arch/arm/boot/dts/meson8.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 93e437c91c61..1bbfc04c3f10 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -158,6 +158,30 @@ gpio-ranges = <&pinctrl_cbus 0 0 120>; }; + sd_a_pins: sd-a { + mux { + groups = "sd_d0_a", "sd_d1_a", "sd_d2_a", + "sd_d3_a", "sd_clk_a", "sd_cmd_a"; + function = "sd_a"; + }; + }; + + sd_b_pins: sd-b { + mux { + groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", + "sd_d3_b", "sd_clk_b", "sd_cmd_b"; + function = "sd_b"; + }; + }; + + sd_c_pins: sd-c { + mux { + groups = "sd_d0_c", "sd_d1_c", "sd_d2_c", + "sd_d3_c", "sd_clk_c", "sd_cmd_c"; + function = "sd_c"; + }; + }; + spi_nor_pins: nor { mux { groups = "nor_d", "nor_q", "nor_c", "nor_cs";