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[91.5.109.245]) by smtp.googlemail.com with ESMTPSA id n189sm5775136wmd.0.2017.07.13.03.31.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Jul 2017 03:31:42 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, khilman@baylibre.com, carlo@caione.org, linux@armlinux.org.uk Subject: [PATCH v3 6/6] ARM: dts: meson8b: add support for booting the secondary CPU cores Date: Thu, 13 Jul 2017 12:31:13 +0200 Message-Id: <20170713103113.21560-7-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.13.2 In-Reply-To: <20170713103113.21560-1-martin.blumenstingl@googlemail.com> References: <20170713103113.21560-1-martin.blumenstingl@googlemail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170713_033201_987311_8964B04D X-CRM114-Status: UNSURE ( 9.03 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, Martin Blumenstingl , robh+dt@kernel.org, arnd@arndb.de MIME-Version: 1.0 Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Carlo Caione Booting the secondary CPU cores involves the following nodes/devices: - SCU (Snoop-Control-Unit, for which we already have a DT node) - a reset line for each CPU core, provided by the reset-controller which is built into the clock-controller - the PMU (power management unit) which controls the power of the CPU cores - a range in the SRAM specifically reserved for booting secondary CPU cores - the "enable-method" which activates booting the secondary CPU cores This adds all required nodes and properties to boot the secondary CPU cores. Signed-off-by: Carlo Caione Signed-off-by: Martin Blumenstingl --- arch/arm/boot/dts/meson8b.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index bc278da7df0d..8826722c6619 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -59,6 +59,8 @@ compatible = "arm,cortex-a5"; next-level-cache = <&L2>; reg = <0x200>; + enable-method = "amlogic,meson8b-smp"; + resets = <&clkc 0>; }; cpu@201 { @@ -66,6 +68,8 @@ compatible = "arm,cortex-a5"; next-level-cache = <&L2>; reg = <0x201>; + enable-method = "amlogic,meson8b-smp"; + resets = <&clkc 1>; }; cpu@202 { @@ -73,6 +77,8 @@ compatible = "arm,cortex-a5"; next-level-cache = <&L2>; reg = <0x202>; + enable-method = "amlogic,meson8b-smp"; + resets = <&clkc 2>; }; cpu@203 { @@ -80,6 +86,8 @@ compatible = "arm,cortex-a5"; next-level-cache = <&L2>; reg = <0x203>; + enable-method = "amlogic,meson8b-smp"; + resets = <&clkc 3>; }; }; @@ -90,6 +98,11 @@ }; /* end of / */ &aobus { + pmu: pmu@e0 { + compatible = "amlogic,meson8b-pmu", "syscon"; + reg = <0xe0 0x18>; + }; + pinctrl_aobus: pinctrl@84 { compatible = "amlogic,meson8b-aobus-pinctrl"; reg = <0x84 0xc>; @@ -157,6 +170,13 @@ }; }; +&ahb_sram { + smp-sram@1ff80 { + compatible = "amlogic,meson8b-smp-sram"; + reg = <0x1ff80 0x8>; + }; +}; + ðmac { clocks = <&clkc CLKID_ETH>; clock-names = "stmmaceth";