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[2003:dc:d3df:c504:d5ed:fadf:ef0c:8dd0]) by smtp.googlemail.com with ESMTPSA id u62sm18070744wmd.5.2017.07.28.14.21.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 28 Jul 2017 14:21:51 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, khilman@baylibre.com, carlo@caione.org, linux@armlinux.org.uk, robh+dt@kernel.org Subject: [PATCH v5 5/6] ARM: dts: meson8: add support for booting the secondary CPU cores Date: Fri, 28 Jul 2017 23:21:37 +0200 Message-Id: <20170728212138.12217-6-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.13.3 In-Reply-To: <20170728212138.12217-1-martin.blumenstingl@googlemail.com> References: <20170728212138.12217-1-martin.blumenstingl@googlemail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170728_142216_920170_CA618940 X-CRM114-Status: UNSURE ( 9.89 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, f.fainelli@gmail.com, Martin Blumenstingl , arnd@arndb.de MIME-Version: 1.0 Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Booting the secondary CPU cores involves the following nodes/devices: - SCU (Snoop-Control-Unit, for which we already have a DT node) - a reset line for each CPU core, provided by the reset-controller which is built into the clock-controller - the PMU (power management unit) which controls the power of the CPU cores - a range in the SRAM specifically reserved for booting secondary CPU cores - the "enable-method" which activates booting the secondary CPU cores This adds all required nodes and properties to boot the secondary CPU cores. Suggested-by: Carlo Caione Signed-off-by: Martin Blumenstingl --- arch/arm/boot/dts/meson8.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index b98d44fde6b6..bf572fb45fe0 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -45,6 +45,7 @@ #include #include +#include #include "meson.dtsi" / { @@ -60,6 +61,8 @@ compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x200>; + enable-method = "amlogic,meson8-smp"; + resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; }; cpu@201 { @@ -67,6 +70,8 @@ compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x201>; + enable-method = "amlogic,meson8-smp"; + resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; }; cpu@202 { @@ -74,6 +79,8 @@ compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x202>; + enable-method = "amlogic,meson8-smp"; + resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; }; cpu@203 { @@ -81,6 +88,8 @@ compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x203>; + enable-method = "amlogic,meson8-smp"; + resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>; }; }; @@ -118,6 +127,11 @@ }; /* end of / */ &aobus { + pmu: pmu@e0 { + compatible = "amlogic,meson8-pmu", "syscon"; + reg = <0xe0 0x8>; + }; + pinctrl_aobus: pinctrl@84 { compatible = "amlogic,meson8-aobus-pinctrl"; reg = <0x84 0xc>; @@ -249,6 +263,13 @@ }; }; +&ahb_sram { + smp-sram@1ff80 { + compatible = "amlogic,meson8-smp-sram"; + reg = <0x1ff80 0x8>; + }; +}; + ðmac { clocks = <&clkc CLKID_ETH>; clock-names = "stmmaceth";