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[2003:dc:d3c2:2104:bdb1:1dc3:65f2:6026]) by smtp.googlemail.com with ESMTPSA id a21sm2764441wrc.64.2017.08.14.14.59.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 14 Aug 2017 14:59:19 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, khilman@baylibre.com, carlo@caione.org, linux@armlinux.org.uk Subject: [PATCH v6 3/6] ARM: smp_scu: allow the platform code to read the SCU CPU status Date: Mon, 14 Aug 2017 23:58:57 +0200 Message-Id: <20170814215900.1032-4-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170814215900.1032-1-martin.blumenstingl@googlemail.com> References: <20170814215900.1032-1-martin.blumenstingl@googlemail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170814_145942_999820_0DEAD0BA X-CRM114-Status: GOOD ( 12.56 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, f.fainelli@gmail.com, arnd@arndb.de, Martin Blumenstingl , robh+dt@kernel.org MIME-Version: 1.0 Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP On Amlogic Meson8 / Meson8m2 (both Cortex-A9) and Meson8b (Cortex-A5) the CPU hotplug code needs to wait until the SCU status of the CPU that is being taken offline is SCU_PM_POWEROFF. Provide a utility function (which can be invoked for example from .cpu_kill()) which allows reading the SCU status of a CPU. While here, replace the magic number 0x3 with a preprocessor macro (SCU_CPU_STATUS_MASK) so we don't have to duplicate this magic number in the new function. Signed-off-by: Martin Blumenstingl --- arch/arm/include/asm/smp_scu.h | 6 ++++++ arch/arm/kernel/smp_scu.c | 18 +++++++++++++++++- 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h index 11e636f33ed9..992b34c4267f 100644 --- a/arch/arm/include/asm/smp_scu.h +++ b/arch/arm/include/asm/smp_scu.h @@ -27,6 +27,7 @@ static inline unsigned long scu_a9_get_base(void) unsigned int scu_get_core_count(void __iomem *); int scu_power_mode(void __iomem *, unsigned int); int scu_cpu_power_enable(void __iomem *, unsigned int); +int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu); #else static inline unsigned int scu_get_core_count(void __iomem *scu_base) { @@ -41,6 +42,11 @@ static inline int scu_cpu_power_enable(void __iomem *scu_base, { return -EINVAL; } +static inline int scu_get_cpu_power_mode(void __iomem *scu_base, + unsigned int logical_cpu) +{ + return -EINVAL; +} #endif #if defined(CONFIG_SMP) && defined(CONFIG_HAVE_ARM_SCU) diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c index 1d549c16b5fc..c6b33074c393 100644 --- a/arch/arm/kernel/smp_scu.c +++ b/arch/arm/kernel/smp_scu.c @@ -21,6 +21,7 @@ #define SCU_STANDBY_ENABLE (1 << 5) #define SCU_CONFIG 0x04 #define SCU_CPU_STATUS 0x08 +#define SCU_CPU_STATUS_MASK GENMASK(1, 0) #define SCU_INVALIDATE 0x0c #define SCU_FPGA_REVISION 0x10 @@ -82,7 +83,8 @@ static int scu_set_power_mode_internal(void __iomem *scu_base, if (mode > 3 || mode == 1 || cpu > 3) return -EINVAL; - val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu) & ~0x03; + val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu); + val &= ~SCU_CPU_STATUS_MASK; val |= mode; writeb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu); @@ -109,3 +111,17 @@ int scu_cpu_power_enable(void __iomem *scu_base, unsigned int cpu) { return scu_set_power_mode_internal(scu_base, cpu, SCU_PM_NORMAL); } + +int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu) +{ + unsigned int val; + int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(logical_cpu), 0); + + if (cpu > 3) + return -EINVAL; + + val = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu); + val &= SCU_CPU_STATUS_MASK; + + return val; +}