diff mbox

[v7,6/6] ARM: dts: meson8b: add support for booting the secondary CPU cores

Message ID 20170917164523.6970-7-martin.blumenstingl@googlemail.com (mailing list archive)
State Accepted
Headers show

Commit Message

Martin Blumenstingl Sept. 17, 2017, 4:45 p.m. UTC 
From: Carlo Caione <carlo@caione.org>

Booting the secondary CPU cores involves the following nodes/devices:
- SCU (Snoop-Control-Unit, for which we already have a DT node)
- a reset line for each CPU core, provided by the reset-controller
  which is built into the clock-controller
- the PMU (power management unit) which controls the power of the CPU
  cores
- a range in the SRAM specifically reserved for booting secondary CPU
  cores
- the "enable-method" which activates booting the secondary CPU cores

This adds all required nodes and properties to boot the secondary CPU
cores.

Signed-off-by: Carlo Caione <carlo@caione.org>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8b.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

Comments

Linus Lüssing Sept. 29, 2017, 11:29 a.m. UTC | #1 
A five hours test run with the stress-ng tool worked fine for this
patchset for me.

stress-ng command:
$ stress-ng -v --sequential 0 -t 120s --exclude sysfs,opcode --metrics

Logfile (6.3MB):
http://metameute.de/~tux/linux/amlogic/stress-ng-odroidc1%2b-with-resmem%2bsmp-log.txt

Tested device:
- Odroid C1+

Tested OS:
- Debian stable (stress-ng 0.07.16)

Tested kernel: v4.14-rc1 plus this patchset plus:
- "ARM: dts: meson: fixing USB support on Meson6, Meson8 and Meson8b"
  https://patchwork.kernel.org/patch/9965871/
- "ARM: dts: meson: enabling the USB Host controller on Odroid-C1/C1+ board"
  https://patchwork.kernel.org/patch/9961565/
- "[RFC] ARM: dts: meson8b: add reserved memory zones"
  https://patchwork.kernel.org/patch/9977479/

Tested kernel config:
- multi_v7_defconfig, except CONFIG_DRM_TEGRA=n (build error otherwise)

 
I had to exclude the sysfs and opcode tests though. The former
created an unhandled kernel paging request. And the latter a
silent freeze after some seconds.

Those two issues seem unrelated to this patchset though,
therefore

Tested-by: Linus Lüssing <linus.luessing@c0d3.blue>
diff mbox

Patch

diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index bc278da7df0d..aaebfcce9073 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -47,6 +47,7 @@ 
 #include <dt-bindings/clock/meson8b-clkc.h>
 #include <dt-bindings/gpio/meson8b-gpio.h>
 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
+#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
 #include "meson.dtsi"
 
 / {
@@ -59,6 +60,8 @@ 
 			compatible = "arm,cortex-a5";
 			next-level-cache = <&L2>;
 			reg = <0x200>;
+			enable-method = "amlogic,meson8b-smp";
+			resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
 		};
 
 		cpu@201 {
@@ -66,6 +69,8 @@ 
 			compatible = "arm,cortex-a5";
 			next-level-cache = <&L2>;
 			reg = <0x201>;
+			enable-method = "amlogic,meson8b-smp";
+			resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
 		};
 
 		cpu@202 {
@@ -73,6 +78,8 @@ 
 			compatible = "arm,cortex-a5";
 			next-level-cache = <&L2>;
 			reg = <0x202>;
+			enable-method = "amlogic,meson8b-smp";
+			resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
 		};
 
 		cpu@203 {
@@ -80,6 +87,8 @@ 
 			compatible = "arm,cortex-a5";
 			next-level-cache = <&L2>;
 			reg = <0x203>;
+			enable-method = "amlogic,meson8b-smp";
+			resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
 		};
 	};
 
@@ -90,6 +99,11 @@ 
 }; /* end of / */
 
 &aobus {
+	pmu: pmu@e0 {
+		compatible = "amlogic,meson8b-pmu", "syscon";
+		reg = <0xe0 0x18>;
+	};
+
 	pinctrl_aobus: pinctrl@84 {
 		compatible = "amlogic,meson8b-aobus-pinctrl";
 		reg = <0x84 0xc>;
@@ -157,6 +171,13 @@ 
 	};
 };
 
+&ahb_sram {
+	smp-sram@1ff80 {
+		compatible = "amlogic,meson8b-smp-sram";
+		reg = <0x1ff80 0x8>;
+	};
+};
+
 &ethmac {
 	clocks = <&clkc CLKID_ETH>;
 	clock-names = "stmmaceth";