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[2003:dc:d3f8:be04:428d:5cff:feb9:9db8]) by smtp.googlemail.com with ESMTPSA id d23sm6269864wma.48.2017.11.17.10.18.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Nov 2017 10:18:12 -0800 (PST) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, gregkh@linuxfoundation.org, linux-serial@vger.kernel.org Subject: [PATCH 2/3] tty: serial: meson: merge the two register sections for AML_UART_CONTROL Date: Fri, 17 Nov 2017 19:18:00 +0100 Message-Id: <20171117181801.29734-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171117181801.29734-1-martin.blumenstingl@googlemail.com> References: <20171117181801.29734-1-martin.blumenstingl@googlemail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171117_181835_507577_5DA436A6 X-CRM114-Status: UNSURE ( 8.75 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: carlo@caione.org, khilman@baylibre.com, Martin Blumenstingl , jslaby@suse.com MIME-Version: 1.0 Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP In the code there are two separate sections which each describe some of the bits in the AML_UART_CONTROL register. Merge these into one section to make the code easier to read. No functional changes intended. Signed-off-by: Martin Blumenstingl --- drivers/tty/serial/meson_uart.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/tty/serial/meson_uart.c b/drivers/tty/serial/meson_uart.c index 78b5d2d15a97..72d425579a4d 100644 --- a/drivers/tty/serial/meson_uart.c +++ b/drivers/tty/serial/meson_uart.c @@ -34,8 +34,15 @@ /* AML_UART_CONTROL bits */ #define AML_UART_TX_EN BIT(12) #define AML_UART_RX_EN BIT(13) +#define AML_UART_TWO_WIRE_EN BIT(15) +#define AML_UART_STOP_BIN_LEN_MASK (0x03 << 16) +#define AML_UART_STOP_BIN_1SB (0x00 << 16) +#define AML_UART_STOP_BIN_2SB (0x01 << 16) +#define AML_UART_PARITY_TYPE BIT(18) +#define AML_UART_PARITY_EN BIT(19) #define AML_UART_TX_RST BIT(22) #define AML_UART_RX_RST BIT(23) +#define AML_UART_CLEAR_ERR BIT(24) #define AML_UART_RX_INT_EN BIT(27) #define AML_UART_TX_INT_EN BIT(28) #define AML_UART_DATA_LEN_MASK (0x03 << 20) @@ -56,15 +63,6 @@ AML_UART_FRAME_ERR | \ AML_UART_TX_FIFO_WERR) -/* AML_UART_CONTROL bits */ -#define AML_UART_TWO_WIRE_EN BIT(15) -#define AML_UART_PARITY_TYPE BIT(18) -#define AML_UART_PARITY_EN BIT(19) -#define AML_UART_CLEAR_ERR BIT(24) -#define AML_UART_STOP_BIN_LEN_MASK (0x03 << 16) -#define AML_UART_STOP_BIN_1SB (0x00 << 16) -#define AML_UART_STOP_BIN_2SB (0x01 << 16) - /* AML_UART_MISC bits */ #define AML_UART_XMIT_IRQ(c) (((c) & 0xff) << 8) #define AML_UART_RECV_IRQ(c) ((c) & 0xff)