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[93.217.177.172]) by smtp.googlemail.com with ESMTPSA id o16sm25843679wmi.29.2017.12.28.14.21.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Dec 2017 14:21:49 -0800 (PST) From: Martin Blumenstingl To: netdev@vger.kernel.org, ingrassia@epigenesys.com Subject: [RFT net-next v3 5/5] net: stmmac: dwmac-meson8b: propagate rate changes to the parent clock Date: Thu, 28 Dec 2017 23:21:28 +0100 Message-Id: <20171228222128.15215-6-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171228222128.15215-1-martin.blumenstingl@googlemail.com> References: <20171228222128.15215-1-martin.blumenstingl@googlemail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20171228_142157_088463_8393EFCF X-CRM114-Status: GOOD ( 10.62 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linus.luessing@c0d3.blue, narmstrong@baylibre.com, Martin Blumenstingl , khilman@baylibre.com, alexandre.torgue@st.com, linux-amlogic@lists.infradead.org, peppe.cavallaro@st.com, jbrunet@baylibre.com MIME-Version: 1.0 Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP On Meson8b the only valid input clock is MPLL2. The bootloader configures that to run at 500002394Hz which cannot be divided evenly down to 25MHz using the m250_div and m25_div clocks. Currently the common clock framework chooses a m250_div of 2 - with the internal fixed "divide by 10" this results in a RGMII clock of 25000120Hz (120Hz above the requested 25MHz). Letting the common clock framework propagate the rate changes up to the parent of m250_mux allows us to get the best possible clock rate. With this patch the common clock framework calculates a rate of very-close-to-250MHz (249999701Hz to be exact) for the MPLL2 clock (which is the mux input). Dividing that by 1 (using m250_div) along with the internal fixed divide-by-10 gives us a RGMII clock of 24999970Hz (which is only 30Hz off the requested 25MHz, compared to 120Hz from u-boot and the vendor driver). SoCs from the Meson GX series are not affected by this change because the input clock is FCLK_DIV2 whose rate cannot be changed (which is fine since it's running at 1GHz, thus it's a multiple of 250MHz). Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic Meson 8b / GXBB DWMAC") Suggested-by: Jerome Brunet Signed-off-by: Martin Blumenstingl --- drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c index d06106417063..9c3cdfef414a 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c @@ -111,7 +111,7 @@ static int meson8b_init_rgmii_clk(struct meson8b_dwmac *dwmac) init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#m250_sel", dev_name(dev)); init.ops = &clk_mux_ops; - init.flags = 0; + init.flags = CLK_SET_RATE_PARENT; init.parent_names = mux_parent_names; init.num_parents = MUX_CLK_NUM_PARENTS;