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[2003:dc:d728:d104:1d61:732:5fba:9a89]) by smtp.googlemail.com with ESMTPSA id l37-v6sm18829626wrl.83.2018.05.01.14.46.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 01 May 2018 14:46:09 -0700 (PDT) From: Martin Blumenstingl To: jbrunet@baylibre.com, narmstrong@baylibre.com, linux-amlogic@lists.infradead.org Subject: [PATCH] clk: meson: meson8b: mark fclk_div gate clocks as CLK_IS_CRITICAL Date: Tue, 1 May 2018 23:45:55 +0200 Message-Id: <20180501214555.11476-1-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.17.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180501_144622_309628_FBB8AAC9 X-CRM114-Status: GOOD ( 10.82 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Martin Blumenstingl , linux-clk@vger.kernel.org MIME-Version: 1.0 Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Until commit 05f814402d6174 ("clk: meson: add fdiv clock gates") we relied on the bootloader to enable the fclk_div clock gates. It turns out that our clock tree is incomplete at least on Meson8b (tested with an Odroid-C1, which uses an RGMII PHY) because after the mentioned commit Ethernet is not working anymore (no RX/TX activity can be seen). At the same time Ethernet was still working on Meson8m2 with a RMII PHY. It is currently not clear which of the fclk_div gates is required for (RGMII) Ethernet operation on Meson8b and why. Mark the fclk_div gates as CLK_IS_CRITICAL so the common clock framework keeps these gates enabled for us until we know which clock is required for Ethernet on Meson8b and which driver has to claim it. Fixes: 05f814402d6174 ("clk: meson: add fdiv clock gates") Signed-off-by: Martin Blumenstingl Tested-by: Kevin Hilman --- drivers/clk/meson/meson8b.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index d0524ec71aad..f3ac099ee22c 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -246,6 +246,7 @@ static struct clk_regmap meson8b_fclk_div2 = { .ops = &clk_regmap_gate_ops, .parent_names = (const char *[]){ "fclk_div2_div" }, .num_parents = 1, + .flags = CLK_IS_CRITICAL, }, }; @@ -270,6 +271,7 @@ static struct clk_regmap meson8b_fclk_div3 = { .ops = &clk_regmap_gate_ops, .parent_names = (const char *[]){ "fclk_div3_div" }, .num_parents = 1, + .flags = CLK_IS_CRITICAL, }, }; @@ -294,6 +296,7 @@ static struct clk_regmap meson8b_fclk_div4 = { .ops = &clk_regmap_gate_ops, .parent_names = (const char *[]){ "fclk_div4_div" }, .num_parents = 1, + .flags = CLK_IS_CRITICAL, }, }; @@ -318,6 +321,7 @@ static struct clk_regmap meson8b_fclk_div5 = { .ops = &clk_regmap_gate_ops, .parent_names = (const char *[]){ "fclk_div5_div" }, .num_parents = 1, + .flags = CLK_IS_CRITICAL, }, }; @@ -342,6 +346,7 @@ static struct clk_regmap meson8b_fclk_div7 = { .ops = &clk_regmap_gate_ops, .parent_names = (const char *[]){ "fclk_div7_div" }, .num_parents = 1, + .flags = CLK_IS_CRITICAL, }, };