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[2003:dc:d732:6200:55ba:2447:d3f4:3559]) by smtp.googlemail.com with ESMTPSA id g15-v6sm6030541wrh.48.2018.07.21.10.37.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 21 Jul 2018 10:37:36 -0700 (PDT) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, khilman@baylibre.com, carlo@caione.org Subject: [PATCH 3/3] ARM: dts: meson8b: add the ARM TWD timer Date: Sat, 21 Jul 2018 19:37:21 +0200 Message-Id: <20180721173721.31361-4-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180721173721.31361-1-martin.blumenstingl@googlemail.com> References: <20180721173721.31361-1-martin.blumenstingl@googlemail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180721_103748_558974_7D20F6A7 X-CRM114-Status: GOOD ( 11.94 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Martin Blumenstingl , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The Meson8B SoC is using four ARM Cortex-A5 cores which come with a "TWD" (Timer-Watchdog) based timer. This adds support for the ARM TWD Timer on this SoC. Suggested-by: Carlo Caione [ rebased patch from Carlo, use IRQ_TYPE_EDGE_RISING instead of IRQ_TYPE_LEVEL_LOW to prevent "GIC: PPI13 is secure or misconfigured" message during boot, use pre-processor macros to specify the IRQ, dropped TWD watchdog node since there's no driver for it anymore ] Signed-off-by: Martin Blumenstingl --- arch/arm/boot/dts/meson8b.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 08f7f6be7254..d0443ae03c72 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -117,6 +117,13 @@ compatible = "arm,cortex-a5-scu"; reg = <0xc4300000 0x100>; }; + + timer@c4300600 { + compatible = "arm,cortex-a5-twd-timer"; + reg = <0xc4300600 0x20>; + interrupts = ; + clocks = <&clkc CLKID_CPU_DIV16>; + }; }; /* end of / */ &aobus {