diff mbox series

[1/3] ARM: dts: meson8b: ec100: enable the Ethernet PHY interrupt

Message ID 20190118234339.16050-2-martin.blumenstingl@googlemail.com (mailing list archive)
State Mainlined
Commit b7d10841e5d7003bb8bc57c122494b4fb47836c0
Headers show
Series ARM: dts: meson8b: ec100: improvements | expand

Commit Message

Martin Blumenstingl Jan. 18, 2019, 11:43 p.m. UTC 
The INTR32 pin of the IP101GR Ethernet PHY is routed to the GPIOH_3 pad
on the SoC.
Enable the interrupt function of the PHY's INTR32 pin to switch it from
it's default "receive error" mode to "interrupt pin" mode.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 arch/arm/boot/dts/meson8b-ec100.dts | 4 ++++
 1 file changed, 4 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts
index cba0006e2de0..1a41d89d1fa5 100644
--- a/arch/arm/boot/dts/meson8b-ec100.dts
+++ b/arch/arm/boot/dts/meson8b-ec100.dts
@@ -169,6 +169,10 @@ 
 		eth_phy0: ethernet-phy@0 {
 			/* IC Plus IP101A/G (0x02430c54) */
 			reg = <0>;
+			icplus,select-interrupt;
+			interrupt-parent = <&gpio_intc>;
+			/* GPIOH_3 */
+			interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
 		};
 	};
 };