| Message ID | 20190325141824.21259-7-narmstrong@baylibre.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Delegated to: | Neil Armstrong |
| Headers | show |
| Series | drm/meson: Add G12A Support | expand |
On Mon, 2019-03-25 at 15:18 +0100, Neil Armstrong wrote: > Amlogic G12A SoC supports the same set of Video Planes, but now > are handled by the new OSD plane blender module. > > This patch uses the same VD1 plane for G12A, using the exact same scaler > and VD11 setup registers, except using the new blender register to > disable the plane. > > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- > drivers/gpu/drm/meson/meson_overlay.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/meson/meson_overlay.c b/drivers/gpu/drm/meson/meson_overlay.c > index b54a22e483b9..bdbf925ff3e8 100644 > --- a/drivers/gpu/drm/meson/meson_overlay.c > +++ b/drivers/gpu/drm/meson/meson_overlay.c > @@ -516,8 +516,14 @@ static void meson_overlay_atomic_disable(struct drm_plane *plane, > priv->viu.vd1_enabled = false; > > /* Disable VD1 */ > - writel_bits_relaxed(VPP_VD1_POSTBLEND | VPP_VD1_PREBLEND, 0, > - priv->io_base + _REG(VPP_MISC)); > + if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) { > + writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL)); > + writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL)); > + writel_relaxed(0, priv->io_base + _REG(VD1_IF0_GEN_REG + 0x17b0)); > + writel_relaxed(0, priv->io_base + _REG(VD2_IF0_GEN_REG + 0x17b0)); Is it possible to add a comment explaining this 0x17b0 value ? > + } else > + writel_bits_relaxed(VPP_VD1_POSTBLEND | VPP_VD1_PREBLEND, 0, > + priv->io_base + _REG(VPP_MISC)); > > } >
On 09/04/2019 10:42, Jerome Brunet wrote: > On Mon, 2019-03-25 at 15:18 +0100, Neil Armstrong wrote: >> Amlogic G12A SoC supports the same set of Video Planes, but now >> are handled by the new OSD plane blender module. >> >> This patch uses the same VD1 plane for G12A, using the exact same scaler >> and VD11 setup registers, except using the new blender register to >> disable the plane. >> >> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> >> --- >> drivers/gpu/drm/meson/meson_overlay.c | 10 ++++++++-- >> 1 file changed, 8 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/meson/meson_overlay.c b/drivers/gpu/drm/meson/meson_overlay.c >> index b54a22e483b9..bdbf925ff3e8 100644 >> --- a/drivers/gpu/drm/meson/meson_overlay.c >> +++ b/drivers/gpu/drm/meson/meson_overlay.c >> @@ -516,8 +516,14 @@ static void meson_overlay_atomic_disable(struct drm_plane *plane, >> priv->viu.vd1_enabled = false; >> >> /* Disable VD1 */ >> - writel_bits_relaxed(VPP_VD1_POSTBLEND | VPP_VD1_PREBLEND, 0, >> - priv->io_base + _REG(VPP_MISC)); >> + if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) { >> + writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL)); >> + writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL)); >> + writel_relaxed(0, priv->io_base + _REG(VD1_IF0_GEN_REG + 0x17b0)); >> + writel_relaxed(0, priv->io_base + _REG(VD2_IF0_GEN_REG + 0x17b0)); > > Is it possible to add a comment explaining this 0x17b0 value ? It's the same register shift as in crtc, will add a define. > >> + } else >> + writel_bits_relaxed(VPP_VD1_POSTBLEND | VPP_VD1_PREBLEND, 0, >> + priv->io_base + _REG(VPP_MISC)); >> >> } >> > > Will fix in a follow-up patch, Neil
diff --git a/drivers/gpu/drm/meson/meson_overlay.c b/drivers/gpu/drm/meson/meson_overlay.c index b54a22e483b9..bdbf925ff3e8 100644 --- a/drivers/gpu/drm/meson/meson_overlay.c +++ b/drivers/gpu/drm/meson/meson_overlay.c @@ -516,8 +516,14 @@ static void meson_overlay_atomic_disable(struct drm_plane *plane, priv->viu.vd1_enabled = false; /* Disable VD1 */ - writel_bits_relaxed(VPP_VD1_POSTBLEND | VPP_VD1_PREBLEND, 0, - priv->io_base + _REG(VPP_MISC)); + if (meson_vpu_is_compatible(priv, "amlogic,meson-g12a-vpu")) { + writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL)); + writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL)); + writel_relaxed(0, priv->io_base + _REG(VD1_IF0_GEN_REG + 0x17b0)); + writel_relaxed(0, priv->io_base + _REG(VD2_IF0_GEN_REG + 0x17b0)); + } else + writel_bits_relaxed(VPP_VD1_POSTBLEND | VPP_VD1_PREBLEND, 0, + priv->io_base + _REG(VPP_MISC)); }
Amlogic G12A SoC supports the same set of Video Planes, but now are handled by the new OSD plane blender module. This patch uses the same VD1 plane for G12A, using the exact same scaler and VD11 setup registers, except using the new blender register to disable the plane. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- drivers/gpu/drm/meson/meson_overlay.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)