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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id z20sm13509543wmf.34.2019.04.23.06.36.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 23 Apr 2019 06:36:53 -0700 (PDT) From: Neil Armstrong To: thierry.reding@gmail.com Subject: [PATCH v2 2/3] pwm: meson: Add clock source configuration for Meson G12A Date: Tue, 23 Apr 2019 15:36:45 +0200 Message-Id: <20190423133646.5705-3-narmstrong@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190423133646.5705-1-narmstrong@baylibre.com> References: <20190423133646.5705-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190423_063656_549666_4A21623B X-CRM114-Status: UNSURE ( 9.89 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-pwm@vger.kernel.org, Neil Armstrong , baylibre-upstreaming@groups.io, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP For the PWM controller in the Meson G12A SoC, the EE domain and AO domain have different clock sources. This patch tries to describe them in the DT compatible data. The two AO PWM controller has different clock source, but the first AO controller (A & B) can reuse the AXG parents name. Signed-off-by: Neil Armstrong Reviewed-by: Martin Blumenstingl --- drivers/pwm/pwm-meson.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 2b03938039b6..bdf1b367e391 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -434,6 +434,24 @@ static const struct meson_pwm_data pwm_axg_ao_data = { .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names), }; +static const char * const pwm_g12a_ao_cd_parent_names[] = { + "aoclk81", "xtal", +}; + +static const struct meson_pwm_data pwm_g12a_ao_cd_data = { + .parent_names = pwm_g12a_ao_cd_parent_names, + .num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_names), +}; + +static const char * const pwm_g12a_ee_parent_names[] = { + "xtal", "hdmi_pll", "fclk_div4", "fclk_div3" +}; + +static const struct meson_pwm_data pwm_g12a_ee_data = { + .parent_names = pwm_g12a_ee_parent_names, + .num_parents = ARRAY_SIZE(pwm_g12a_ee_parent_names), +}; + static const struct of_device_id meson_pwm_matches[] = { { .compatible = "amlogic,meson8b-pwm", @@ -455,6 +473,18 @@ static const struct of_device_id meson_pwm_matches[] = { .compatible = "amlogic,meson-axg-ao-pwm", .data = &pwm_axg_ao_data }, + { + .compatible = "amlogic,meson-g12a-ee-pwm", + .data = &pwm_g12a_ee_data + }, + { + .compatible = "amlogic,meson-g12a-ao-pwm-ab", + .data = &pwm_axg_ao_data + }, + { + .compatible = "amlogic,meson-g12a-ao-pwm-cd", + .data = &pwm_g12a_ao_cd_data + }, {}, }; MODULE_DEVICE_TABLE(of, meson_pwm_matches);